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Alligator Clips, Back Probe Pins, Piercing Clips, Test Clips, Test Probes, Test Leads
Packaging
Pouch
Lead Free Status
Lead Free
RoHS Status
RoHS Compliant
Other Names
6530 6530
6530 General Description
The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.
The GVT7164D64 SRAM integrates 65,536x64 SRAM cells with advanced synchronous peripheral circuitry and a 2- bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edgetriggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE#), depth-expansion chip enables (CE2#, CE3#, CE2 and CE3), burst control inputs (ADSC#, ADSP#, and ADV#), write enables (BW1# to BW8#,and BWE#), and global write (GW#).
Asynchronous inputs include the output enable (OE#) and burst mode control (MODE). The data outputs (Q), enabled by OE#, are also asynchronous.
Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#).
Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one to eight bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1# controls DQ1-DQ8. BW2# controls DQ9- DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25- DQ32. BW5# controls DQ33-DQ40. BW6# controls DQ41- DQ48. BW7# controls DQ49-DQ56. BW8# controls DQ57- DQ64. BW1#, BW2#, BW3#, BW4#, BW5#, BW6#, BW7#, and BW8# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written.
The GVT7164D64 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, PentiumTM, 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus.
6530 Maximum Ratings
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN .................................................................-0.5V to +6V Storage Temperature (plastic) ...................-55oC to +150o Junction Temperature ...............................................+150o Power Dissipation .......................................................1.6W Short Circuit Output Current .....................................100mA *Stresses greater than those listed uunder "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6530 Features
• Fast access times: 5, 6, and 7ns • Fast clock speed: 100, 83, and 66 MHz • Provide high performance 3-1-1-1 access rate • Fast OE# access times: 5, 6, and 7ns • Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) • 3.3V -5% and +10% core power supply, 2.5V or 3.3V I/O supply • 5V tolerant inputs except I/O's • Clamp diodes to VSS at all inputs and outputs • Common data inputs and data outputs • BYTE WRITE ENABLE and GLOBAL WRITE control • Four chip enables for depth expansion and one chip enable for address pipeline • Address, control, input, and output pipeline registers • Internally self-timed WRITE CYCLE • Burst sequence control pins MODE (interleaved or linear burst sequence) • Automatic power-down for portable applications • ZZ pin for snooze control • High density, high speed packages • High 30pF output drive capability at rated access time