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7 pcs in 7 different lengths, 1 ft ~ 10 ft. lengths
Packaging
-
Lead Free Status
Lead Free
RoHS Status
RoHS Compliant
Other Names
6534 6534
6534 General Description
The GVT72128A8 is organized as a 131,072 x 8 SRAM using a four-transistor memory cell with a high performance,silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology.
This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#) and output enable (OE#) with this organization.
Writing to these devices is accomplished when write enable (WE#) and chip enable (CE#) inputs are both LOW.Reading is accomplished when (CE#) and (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
6534 Maximum Ratings
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN .......................................................-0.5V to VCC+0.5V Storage Temperature (plastic) .................-55oC to +125o Junction Temperature .............................................+125o Power Dissipation .....................................................1.2W Short Circuit Output Current ....................................50mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6534 Features
• Fast access times: 10, 12, 15and 20ns • Fast OE# access times: 5, 6, 7 and 8ns • Single +5V +10% power supply • Fully static -- no clock or timing strobes necessary • All inputs and outputs are TTL-compatible • Three state outputs • Center power and ground pins for greater noise immunity • JEDEC standard for functionality and revolutionary pinout • Easy memory expansion with CE# and OE# options • Automatic CE# power down • High-performance, low-power consumption, CMOS double-poly, double-metal process