6533

The 6533 is organized as a 262,144 x 4 SRAM using a four-transistor memory cell with a high performance,silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology.

Static design of 6533 eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#) and output enable (OE#) with this organization.

Writing to 6533 is accomplished when write enable (WE#) and chip enable (CE#) inputs are both LOW.Reading is accomplished when (CE#) and (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.