MFG:FCI Category:Connectors Package Cooled:SMD D/C:06
6-5179010-0, 6518, 65182-001LF Datasheet download
Category: Connectors
MFG: FCI
Package Cooled: SMD
D/C: 06
Description: BP LATCH LF
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The Galvantech Synchronous Burst SRAM family mploys high-speed, low power CMOS designs using dvanced triple-layer polysilicon, double-layer metal echnology. Each memory cell consists of four transistors and wo high valued resistors.
The GVT71256F18 SRAM integrates 262,144x18 RAM cells with advanced synchronous peripheral circuitry nd a 2-bit counter for internal burst operation. All ynchronous inputs are gated by registers controlled by a ositive-edge-triggered clock input (CLK). The synchronous nputs include all addresses, all data inputs, address-pipelining hip enable (CE#), depth-expansion chip enables (CE2# and E2), burst control inputs (ADSC#, ADSP#, and ADV#),write enables (WEL#, WEH#, and BWE#), and global write GW#).
Asynchronous inputs include the output enable (OE#) nd burst mode control (MODE). The data outputs (Q), nabled by OE#, are also asynchronous.
ddresses and chip enables are registered with either ddress status processor (ADSP#) or address status controller ADSC#) input pins. Subsequent burst addresses can be nternally generated as controlled by the burst advance pin ADV#).
Address, data inputs, and write controls are registered onchip o initiate self-timed WRITE cycle. WRITE cycles can e one to four bytes wide as controlled by the write control nputs. Individual byte write allows individual byte to be ritten. WEL# controls DQ1-DQ8 and DQP1. WEH# ontrols DQ9-DQ16 and DQP2. WEL#, and WEH# can be ctive only with BWE# being LOW. GW# being LOW causes ll bytes to be written. WRITE pass-through capability allows ritten data available at the output for the immediately next EAD cycle. This device also incorporates pipelined enable ircuit for easy depth expansion without penalizing system erformance.
The GVT71256F18 operates from a +3.3V core power upply and all outputs operate on a +2.5V supply. All inputs nd outputs are JEDEC standard JESD8-5 compatible. The evice is ideally suited for 486, PentiumTM, 680x0, and owerPCTM systems and for systems that are benefited from a ide synchronous data bus.
Voltage on VCC Supply Relative to VSS....... -0.5V to +4.6V
VIN .......................................................... -0.5V to VCC+0.5V
Storage Temperature (plastic) .......................-55oC to +150o
Junction Temperature ...................................................+150o
Power Dissipation ...........................................................1.0W
Short Circuit Output Current ..........................................50mA
*Stresses greater than those listed uunder "Absolute Maximum atings" may cause permanent damage to the device.This is a stress ating only and functional operation of the device at these or any ther conditions above those indicated in the operational sections of his specification is not implied. Exposure to absolute maximum ating conditions for extended periods may affect reliability.
| Technical/Catalog Information | 65182-001LF |
| Vendor | FCI |
| Category | Connectors |
| Accessory Type | Latch |
| For Use With/Related Products | - |
| Specifications | Locking |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | 65182 001LF 65182001LF |
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