Features: • Fast access times: 8, 9, 10, and 12ns
• Fast clock speed: 83, 66, and 50 MHz
• Provide high performance 2-1-1-1 access rate
• Fast OE# access times: 5 and 6ns
• Single +5V +5% power supply
• 3.3V I/O compatible
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte writeable via dual write enables
• Address, data and control registers
• Internally self-timed WRITE CYCLE
• Automatic power-down for low power applications
• High board density 52-lead PLCC packagesPinout
SpecificationsVoltage on VCC Supply Relative to VSS... ....-0.5V to +7.0V
VIN ...........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ......................-55oC to +125o
Junction Temperature ..................................................+125o
Power Dissipation ..................................................... ...1.6W
Short Circuit Output Current ..........................................30mA
*Stresses greater than those listed under "Absolute Maximum atings" may cause permanent damage to the device.This is a stress ating only and functional operation of the device at these or any ther conditions above those indicated in the operational sections of his specification is not implied. Exposure to absolute maximum ating conditions for extended periods may affect reliability.
DescriptionThe Galvantech Synchronous Burst SRAM family of 6524 employs high-speed, low power CMOS designs usingadvanced double-layer polysilicon, double-layer metaltechnology. Each memory cell consists of four transistors andtwo high valued resistors.
The 6524 SRAM integrates 65,536 x18 SRAMcells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronousnputs are gated by registers controlled by a positive-edgetriggeredclock input (CLK). The synchronous inputs includeall addresses, all data inputs, chip enable (CE#), burst controlinputs (ADSC#, ADSP#, and ADV#), and write enables(WEL# and WEH#).
Asynchronous input of 6524 includes the output enable (OE#).The data outputs (DQ), enabled by OE#, are alsoasynchronous.
Addresses and chip enables of 6524 are registered with eitheraddress status processor (ADSP#) or address status controller(ADSC#) input pins. Subsequent burst addresses can beinternally generated as controlled by the burst advance pin(ADV#).
Address, data inputs, and write controls of 6524 are registered onchipto initiate self-timed WRITE cycle. WRITE cycles canbe one or two bytes wide as controlled by the write controlinputs. Individual byte enables allow individual bytes to bewritten. WEL# controls DQ1-DQ8 and DQP1. WEH#controls DQ9-DQ16 and DQP2.
The 6524 operates from a +5V power supply.All inputs and outputs are TTL-compatible. The device isideally suited for 486, PentiumTM, 680x0, and for systems that re benefited from a wide synchronous data bus.
6524 Data Sheet
