Features: • Fast access times: 5.5, 6, and 7ns
• Fast clock speed: 100, 75, and 66MHz
• Provide high performance 3-1-1-1 access rate
• Fast OE# access times: 5.5, 6, and 7ns
• Optimal for depth expansion (one cycle chip deselect to liminate bus contention)
• Single +3.3V -5% and +10% power supply
• Clamp diodes to VSSQ at all inputs and outputs
• 5V tolerant inputs except I/O's
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL WRITE control
• Three chip enables for depth expansion and address ipeline
• Address, control, input, and output pipeline registers
• Internally self-timed WRITE CYCLE
• WRITE pass-through capability
• ZZ snooze mode control
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High density, high speed packages
• Low capacitive bus loading
• High 30pF output drive capability at rated access timePinout
SpecificationsVoltage on VCC Supply Relative to VSS........ -5V to +4.6V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ......................-55oC to +125o
Junction Temperature ..................................................+125o
Power Dissipation ..........................................................1.4W
Short Circuit Output Current .......................................100mA
*Stresses greater than those listed under "Absolute MaximumRatings" may cause permanent damage to the device.This is a stressrating only and functional operation of the device at these or anyother conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum ating conditions for extended periods may affect reliability.DescriptionThe Galvantech Synchronous Burst SRAM family of 6522 employs high-speed, low power CMOS designs usingadvanced double-layer polysilicon, double-layer metaltechnology. Each memory cell consists of four transistors andtwo high valued resistors.
The 6522 SRAM integrates 32768x32 SRAMcells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronousinputs are gated by registers controlled by a positive-edgetriggeredclock input (CLK). The synchronous inputs includeaddresses, data inputs, address-pipelining chip enable (CE#),depth-expansion chip enables (CE2# and CE2), burst controlinputs (ADSC#, ADSP#, and ADV#), write enables (BW1#,BW2#, BW3#, BW4#,and BWE#), and global write (GW#).Asynchronous inputs include the output enable (OE#),burst mode control (MODE), and sleep mode control (ZZ).The data outputs (Q), enabled by OE#, are also asynchronous.
Addresses and chip of 6522 are registered with eitheraddress status processor (ADSP#) or address status controller(ADSC#) input pins. Subsequent burst addresses can beinternally generated as controlled by the burst advance pin(ADV#).
Addresses, data inputs, and write controls of 6522 are registeredon-chip to initiate self-timed WRITE cycle. WRITE cyclescan be one to four bytes wide as controlled by the writecontrol inputs. Individual byte write allows individual byte tobe written. BW1# controls DQ1-DQ8. BW2# controls DQ9-DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25-DQ32. BW1#, BW2# BW3#, and BW4# can be active onlywith BWE# being LOW. GW# being LOW causes all bytes tobe written. WRITE pass-through capability allows writtendata available at the output for the immediately next READcycle. This device also incorporates pipelined enable circuitfor easy depth expansion without penalizing systemperformance.
The 6522 operates from a +3.3V power supply.All inputs and outputs are TTL-compatible. The device is deally suited for 486, PentiumTM, 680x0, and PowerPCTM ystems and for systems that are benefited from a wide ynchronous data bus.
6522 Data Sheet
