Features: • Fast access times: 9, 10, and 12ns
• Fast clock speed: 66, and 50 MHz
• Provide high performance 2-1-1-1 access rate
• Fast OE# access times: 5 and 6ns
• Single +3.3V -5% and +10% power supply
• 5V tolerant inputs except I/O's
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL WRITE control
• Three chip enables for depth expansion and address ipeline
• Address, data and control registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High density, high speed packages
• Low capacitive bus loading
• High 30pF output drive capability at rated access timePinout
SpecificationsVoltage on VCC Supply Relative to VSS.. -0.5V to +4.6V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) .....................-55oC to +125o
Junction Temperature .................................................+125o
Power Dissipation .........................................................1.4W
Short Circuit Output Current ......................................100mA
*Stresses greater than those listed under "Absolute Maximum atings" may cause permanent damage to the device.This is a stress ating only and functional operation of the device at these or any ther conditions above those indicated in the operational sections of his specification is not implied. Exposure to absolute maximum ating conditions for extended periods may affect reliability.
DescriptionThe Galvantech Synchronous Burst SRAM familyemploys high-speed, low power CMOS designs usingadvanced double-layer polysilicon, double-layer metalechnology. Each memory cell consists of four transistors andtwo high valued resistors.
The 6521 SRAM integrates 32768x36 SRAMcells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronousinputs are gated by registers controlled by a positive-edgetriggeredclock input (CLK). The synchronous inputs includeall addresses, all data inputs, address-pipelining chip enable(CE#), depth-expansion chip enables (CE2# and CE2), burst ontrol inputs (ADSC#, ADSP#, and ADV#), write enables BW1#, BW2#, BW3#, BW4#,and BWE#), and global write(GW#).
Asynchronous inputs of 6521 include the output enable (OE#),burst mode control (MODE), and sleep mode control (ZZ). he data outputs (Q), enabled by OE#, are also asynchronous. ddresses and chip enables are registered with either ddress status processor (ADSP#) or address status controller ADSC#) input pins. Subsequent burst addresses can be nternally generated as controlled by the burst advance pin ADV#).
ddress, data inputs, and write controls of 6521 are registered onchip o initiate self-timed WRITE cycle. WRITE cycles can e one to four bytes wide as controlled by the write control nputs. Individual byte write allows individual byte to be ritten. BW1# controls DQ1-DQ8 and DQP1. BW2# controls Q9-DQ16 and DQP2. BW3# controls DQ17-DQ24 and QP3. BW4# controls DQ25-DQ32 and DQP4. BW1#, W2# BW3#, and BW4# can be active only with BWE# eing LOW. GW# being LOW causes all bytes to be written.
The G6521 operates from a +3.3V power supply. ll inputs and outputs are TTL-compatible. The device is deally suited for 486, PentiumTM, 680x0, and PowerPCTM ystems and for systems that are benefited from a wide ynchronous data bus.
6521 Data Sheet
