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ZL30101QD, ZL30102, ZL30105

Table of contents:
Info of ZL30101QD
Info of ZL30102
Info of ZL30105

ZL30101QD, ZL30102, ZL30105 Selling Leads, Datasheet

MFG:ZARLINK Package Cooled:TQFP D/C:2008

ZL30101QD, ZL30102, ZL30105 Datasheet download

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Part Number: ZL30101QD

MFG: ZARLINK

Package Cooled: TQFP

D/C: 2008

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ZL30102 General Description

The ZL30102 DS1/E1 Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for DS1/E1 transmission equipment deploying redundant network clocks.

The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to another system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between the primary aster-clock and secondary master clock outputs even in the presence of high network jitter.

The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

ZL30102 Maximum Ratings

	Parameter	Symbol	Min.	Max.	UNIT
1	Supply voltage	V _{DD_R}	-0.5	4.6	V
2	Core supply voltage	V _{CORE_R}	-0.5	2.5	V
3	Voltage on any digital pin	V_PIN	-0.5	6	V
4	Voltage on OSCi and OSCo pin	V_OSC	-0.3	VDD + 0.3	V
5	Current on any pin	I_PIN		30	mA
6	Storage temperature	T_ST	-55	125
7	TQFP 64 pin package power dissipation	P_PD		500	mW
8	ESD rating	V_ESD		2	kV

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.

ZL30102 Features

• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock
• Supports Telcordia GR-1244-CORE Stratum 4 and 4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
• Simple hardware control interface
• Manual and Automatic hitless reference switching
• Accepts three input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1x10-7
• Provides Lock, Holdover and selectable Out of Range indication
• Attenuates wander from 1.8 Hz
• Less than 0.6 nspp intrinsic jitter on all output clocks
• External master clock source: Clock Oscillator or Crystal

ZL30102 Typical Application

• Synchronization and timing control for multi-trunk DS1/ E1 terminal systems such as DSLAMs, Gateways and PBXs
• Clock and frame pulse source for H.110 CT Bus, ST-BUS, GCI and other time division multiplex (TDM) buses

ZL30102 Connection Diagram

ZL30105 General Description

The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks.

The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to a system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the master-clock and slave-clock outputs even in the presence of high network jitter.

The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications.

ZL30105 Maximum Ratings

	Parameter	Symbol	Min.	Max.	UNIT
1	Supply voltage	V _{DD_R}	-0.5	4.6	V
2	Core supply voltage	V _{CORE_R}	-0.5	2.5	V
3	Voltage on any digital pin	V_PIN	-0.5	6	V
4	Voltage on OSCi and OSCo pin	V_OSC	-0.3	VDD + 0.3	V
5	Current on any pin	I_PIN		30	mA
6	Storage temperature	T_ST	-55	125
7	TQFP 64 pin package power dissipation	P_PD			mW
8	ESD rating	V_ESD		2	kV

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.

ZL30105 Features

• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock
• Supports ITU-T G.813 option 1, G.823 for 2048 kbs and G.824 for 1544 kbs interfaces
• Supports Telcordia GR-1244-CORE Stratum 3/4/4E
• Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
• Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
• Provides a range of clock outputs: 1.544 MHz (DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz, and 19.44 MHz (SDH), and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz, and a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
• Holdover frequency accuracy of 1x10-8
• Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz
• Less than 20 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
• Less than 0.6 nspp intrinsic jitter on all output clocks and frame pulses
• Manual or Automatic hitless reference switching
• Provides Lock, Holdover and selectable Out of Range indication
• Simple hardware control interface
• Selectable external master clock source: Clock Oscillator or Crystal

ZL30105 Typical Application

• Synchronization and timing control for multi-trunk SDH and T1/E1 systems such as DSLAMs, Gateways and PBXs
• Clock and frame pulse source for AdvancedTCA™- and other time division multiplex (TDM) buses

ZL30105 Connection Diagram

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