ZL30106

• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
• Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
• Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
• Provides a range of clock outputs:
- 2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
• Provides automatic entry into Holdover and return from Holdover
• Manual and automatic hitless reference switching
• Provides lock, holdover and accurate reference fail indication
• Selectable loop filter bandwidth of 29 Hz or 922 Hz
• Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253- CORE OC-3 and G.813 STM-1 specifications
• Less than 0.6 nspp intrinsic jitter on all PDH output locks and frame pulses
• Selectable external master clock source: clock oscillator or crystal
• Simple hardware control interface

The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards.

The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs.

The ZL30106 output clocks wander and jitter generation are compliant with the associated transport medium specifications.