ZL30102

• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock
• Supports Telcordia GR-1244-CORE Stratum 4 and 4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
• Simple hardware control interface
• Manual and Automatic hitless reference switching
• Accepts three input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1x10-7
• Provides Lock, Holdover and selectable Out of Range indication
• Attenuates wander from 1.8 Hz
• Less than 0.6 nspp intrinsic jitter on all output clocks
• External master clock source: Clock Oscillator or Crystal

The ZL30102 DS1/E1 Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for DS1/E1 transmission equipment deploying redundant network clocks.

The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to another system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between the primary aster-clock and secondary master clock outputs even in the presence of high network jitter.

The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.