ZL30106QDG1, ZL30107GGG2, ZL30108 Selling Leads, Datasheet
MFG:ZARLINK Package Cooled:QFP64 D/C:0838+
ZL30106QDG1, ZL30107GGG2, ZL30108 Datasheet download
Part Number: ZL30106QDG1
MFG: ZARLINK
Package Cooled: QFP64
D/C: 0838+
ZL30106QDG1, ZL30107GGG2, ZL30108
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Info of ZL30106QDG1
Info of ZL30107GGG2
Info of ZL30108
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About ZL30100
PDF/DataSheet Download
Datasheet: ZL30100
File Size: 574385 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
About ZL30100
PDF/DataSheet Download
Datasheet: ZL30100
File Size: 574385 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
About ZL30108
PDF/DataSheet Download
Datasheet: ZL30108
File Size: 544416 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
ZL30108 General Description
The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards.
The ZL30108 generates a SONET/SDH clock and framing signals that are phase locked to one of two backplane or network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs.
The ZL30108 output clock's wander and jitter generation are compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications.
ZL30108 Maximum Ratings
| Parameter | Symbol | Min. | Max. | UNIT | |
| 1 | Supply voltage | V DD_R | -0.5 | 4.6 | V |
| 2 | Core supply voltage | V CORE_R | -0.5 | 2.5 | V |
| 3 | Voltage on any digital pin | VPIN | -0.5 | 6 | V |
| 4 | Voltage on OSCi and OSCo pin | VOSC | -0.3 | VDD + 0.3 | V |
| 5 | Current on any pin | IPIN | 30 | mA | |
| 6 | Storage temperature | TST | -55 | 125 | |
| 7 | Package power dissipation | PPD | 195 | mW | |
| 8 | ESD rating | VESD | 2k | V |
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
ZL30108 Features
• Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
• Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
• Provides a 19.44 MHz (SONET/SDH) clock output
• Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
• Provides automatic entry into Holdover and return from Holdover
• Hitless reference switching
• Provides lock and accurate reference fail indication
• Loop filter bandwidth of 29 Hz or 14 Hz
• Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
• Less than 0.5 nspp intrinsic jitter on output frame pulses
• External master clock source: clock oscillator or crystal
• Simple hardware control interface
ZL30108 Typical Application
• Line card synchronization for SONET/SDH systems
ZL30108 Connection Diagram
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