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ZL30109, ZL30110, ZL30110L

Table of contents:
Info of ZL30109
Info of ZL30110
Info of ZL30110L

ZL30109, ZL30110, ZL30110L Selling Leads, Datasheet

MFG:ZARLINK Package Cooled:07+08+ D/C:QFP-64

ZL30109, ZL30110, ZL30110L Datasheet download

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Part Number: ZL30109

MFG: ZARLINK

Package Cooled: 07+08+

D/C: QFP-64

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ZL30109 General Description

The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44 MHz output makes the ZL30109 also suitable for SDH line card applications.

The ZL30109 generates a 19.44 MHz clock and ST-BUS and TDM bus clocks and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.

The ZL30109 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

ZL30109 Maximum Ratings

	Parameter	Symbol	Min.	Max.	UNIT
1	Supply voltage	V _{DD_R}	-0.5	4.6	V
2	Core supply voltage	V _{CORE_R}	-0.5	2.5	V
3	Voltage on any digital pin	V_PIN	-0.5	6	V
4	Voltage on OSCi and OSCo pin	V_OSC	-0.3	VDD + 0.3	V
5	Current on any pin	I_PIN		30	mA
6	Storage temperature	T_ST	-55	125
7	TQFP 64 pin package power dissipation	P_PD		500	mW
8	ESD rating	V_ESD		2	kV

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.

ZL30109 Features

• Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
• Simple hardware control interface
• Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
• Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz, 19.44 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
• Holdover frequency accuracy of 1.5 x 10-7
• Lock, Holdover and selectable Out of Range indication
• Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
• Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with OC-3 and STM-1 jitter specifications
• Less than 0.6 nspp intrinsic jitter on all output clocks
• External master clock source: clock oscillator or crystal

ZL30109 Typical Application

• Synchronization and timing control for DSLAM, Gateway and PBX systems that require Stratum 4/4E timing
• Line Card synchronization for SDH/PDH applications
• Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses

ZL30109 Connection Diagram

ZL30110 General Description

The ZL30110 clock rate conversion digital phaselockedloop (DPLL) provides accurate and reliable frequency conversion.

The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator.

In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.

ZL30110 Maximum Ratings

	Parameter	Symbol	Min.	Max.	Units
1	Supply voltage	V_{DD_R}	-0.5	4.6	V
2	Core supply voltage	V_{CORE_R}	-0.5	2.5	V
3	Voltage on any digital pin	V_PIN	-0.5	6	V
4	Voltage on OSCi and OSCo pin	V_OSC	-0.3	VDD+0.3	V
5	Current on any pin	I_PIN		30	mA
6	Storage temperature	T_ST	-55	125
7	ESD rating	V_ESD		K	V

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.

ZL30110 Features

• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
• Provides a range of output clocks:
• 65.536 MHz TDM clock locked to the input reference
• General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
• General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator
• Provides DPLL lock and reference fail indication
• Automatic free run mode on reference fail
• DPLL bandwidth of 922 Hz for all rates of inputreference and 58 Hz for an 8 kHz input reference
• Less than 5 psecrms on 25 MHz outputs, and less than 0.6 nspp intrinsic jitter on the all other outputs
• Minimal input to output and output to output skew
• 25 MHz external master clock source: clock oscillator or crystal
• Simple hardware control interface

ZL30110 Typical Application

• Clock rate conversion PLL for Telecommunication Equipment
• Small/Medium Enterprise Router / Gateway
• Broadband access (xPON/xDSL) CPE gateway

ZL30110 Connection Diagram

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