CD_IGNITION

Published:2009/6/28 21:50:00 Author:May

Uses master oscillator-power amplifier type of DC/DC converter in which two sections of triple 3-input NANDgate serve as 10 kHz square-wave MVBR feeding class B PNP/ NPN power amplifier through two-gate driver. Remaining two gates are used as logic invert-ers. Secondary of T1 has t5.24 meters of No. 26 in six bankwindings, with 20tums No. 14 added and center-tapped for primary. T2 is unshielded iron-core RF choke, 30-100 pH, whh several turns wound over it for secondary. When main 20-A SCR fires, T2 develops oscillation burst for firing sensitive gate-Iatching SCR. Storage ca-pacitor energy is then dumped into ignition coil primary through power SCR.-K. W. Robbins, CD Ignition System, 73 Magazine, May 1974, p 17and19.   (View)

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74 Series digital circuit of 74191, 74LS191 preset 4-bit synchronous reversible binary counter(with mode control)

Published:2011/7/31 23:05:00 Author:Lucas | Keyword: 74 Series, digital circuit , preset 4-bit synchronous , reversible binary counter, mode control

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74 Series digital circuit of 74LS168A/169A preset 4-bit synchronous reversible counter

Published:2011/7/28 22:42:00 Author:Lucas | Keyword: 74 Series , digital circuit , preset 4-bit synchronous , reversible counter

168 is preset carry lookahead reversible decimal counter; 169 is preset carry lookahead reversible binary counter; count and preset are fully synchronized; it can be carry lookahead when fast counting; it can be used for n-bit binary cascade output; the clock circuit is fully independent.   (View)

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Simple_8_differential_channel_ADC

Published:2009/7/25 4:46:00 Author:Jessie

Figure 9-11 shows the ADC0816/17 connected to provide for an ADC with eight differential inputs. The differential inputs are implemented in software. All 16 channels are paired into positive and negative inputs. Then the control logic or microprocessor converts each channel of a differential pair, loads each result, then subtracts the two results. This method requires two single-ended conversions to do one differential conversiqn. As a result, the effective differential-conver sion time is twice that of a single channel, or a little more than 200 μs (assuming a clock of 640 kHz). The differential inputs should be stable throughout both conversions to produce accurate results. NATIONAL SEMICONDUCTOR, APPLICATION NorE 258, 1994, P. 597.   (View)

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Simple_32_channel_ADC

Published:2009/7/25 4:44:00 Author:Jessie

Figure 9-10 shows the ADC0816/17 connected to provide for 32-channel conversion. Such a configuration is possible because of the EC pin, which is actually a multiplexer enable. When the EC signal is low, all switches are inhibited so that another signal can be applied to the comparator input. Additional channels can be implemented as necessary. A total of five address lines are required to address the 32 channels. The lower four bits are applied directly to the A, B, C, and D inputs, All four bits are also applied to an MM74C174 flip-flop which is used as an address latch for the two CD4051s. The 1Q, 2Q, and 3Q outputs of the flip-flop feed the CD4051 address inputs. The 4Q and 5Q outputs are gated to form enable signals for each CD4051. Output 5Q is also applied at the EC input (after inversion) to enable the ADC multiplexer. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 596.   (View)

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Eliminating_input_gain_adjustments

Published:2009/7/25 4:43:00 Author:Jessie

Figures 9-8 and 9-9 show the ADC0816/17 connected to eliminate gain adjustments on the analog input signals. This is done by varying the ADC REF+ and REF- voltages to get various full-scale ranges Typically, the reference voltages can be varied from 5 V to about 0.5 V to accommodate various input voltages. However, there is a restriction: the center of the reference voltage must be within 10.1 V of mid-supply. The reason for this restriction is that the reference ladder is tapped by an N-channel or P-channel MOSFET switch tree (Fig. 9-1), Offsetting the voltage at the center of the switch tree from VCC2 causes the transistors to turn off at the wrong point, resulting in inaccurate and erratic conversions. However, if properly applied, this method can reduce parts count and eliminate extra power Supplies for the input buffers. In the supply-centered reference circuit of Fig. 9-8, R1 and R2 offset REF+ and REF- from VCC and ground. An LM336-2.5 is shown, but any reference betueen 0.5 V and 5 V can be used. For odd reference values, use the op-amp circuit of Fig. 9-9. Single-supply op amps, such as the LM324 or LM10, can be used. R1, R2, and R3 form a resistor divider in which R1 and R3 center the reference at VCC2 and R2 can be varied to get the proper reference magnitude. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 595.   (View)

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74 Series digital circuit of 74167 BCD synchronization coefficient multiplier

Published:2011/7/29 1:14:00 Author:Lucas | Keyword: 74 Series, digital circuit, BCD , synchronization coefficient multiplier

The fractional frequency has the fixed frequency or variable frequency; the typical maximum clock frequency is 32MHz. When the clear strobe sets to 9 and it allows the input to be low, the counter starts to work. 1. The status of clock and strobe has the effect on the logic level Y and Z, for example, unit/ cascade is low, the output Y remains high. 2. Each factor of the factor inputs is set to constant, but also can be a variable factor input. 3. The input conditions have been greater than the decimal input range. 4. Unit/cascade can be used to disable the output terminal Y.   (View)

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DAC_controlled_ctmplifier

Published:2009/7/25 5:34:00 Author:Jessie

Figure 9-36 shows a DAC1000 connected to control the output of an LF351 amplifier. In this circuit, the DAC is used as the feedback element for an inverting amplifier. The R-2R ladder digitally adjusts the amount of output signal fed back to the amplifier summing junction. The feedback resistance can be thought of as varying from about 15 kΩ to infinity when the input code changes from full-scale to zero. The internal feedback resistor is used as the amplifier input resistor. When the input code is all 0s, the feedback loop is opened and the op-amp output saturates. NATIONAL SEMICONDUCTOR, APPLICATION NorE 271, 1994, P. 667.   (View)

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DAC_with_bipolar_output_from_a_fixed_reference

Published:2009/7/25 5:33:00 Author:Jessie

Figure 9-35 shows a DAC0830 connected to provide a bipolar output from a fixed reference voltage. This connection is made with a second op amp in the analog-output circuit. In effect, the circuit gives sign significance to the MSB of the digital-input word, allowing four-quadrant multiplication of the reference voltage. The polarity of the reference can still be reversed (or can be an ac signal) to realize full four-quadrant multiplication. NATIONAL SEMICONDUCTOR, APPLICATION Now 271, 1994 P. 666.   (View)

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DAC_connected_for_single_supply_operation

Published:2009/7/25 5:31:00 Author:Jessie

Figure 9-34 shows a DAC1000 connected for single-supply operation. The R-2R ladder can be operated as a voltage-switching network to prevent the output-voltage inversion that is so common in the current-switching mode. In this circuit, the reference voltage is applied to the IOUT 1 terminal and is attenuated by the R-2R ladder in proportion to the applied code. The voltage is then output to the VREF terminal with no phase inversion. To ensure linear operation in single-supply modes, the applied voltage must be kept less than 3 V for 10-bit DACs, or less than 5 V for 8-bit DACs. The supply voltage to the DAC must be at least 10 V more positive than the reference voltage to ensure that the CMOS ladder switches have enough voltage Qverdrive to fully turn on. An external op amp can be added to provide gain to the DAC output voltage for a wide overall output span. This circuit provides generally good linearity for 8-bit and 8-bit DACs, but can have a problem with 12-bit DACs (because of the very low reference required). If 12-bit operation is desired, use a DAC specifically designed for single-supply operation. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 271, 1994, P. 666.   (View)

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DAC_with_level_shifted_output

Published:2009/7/25 5:30:00 Author:Jessie

Figure 9-33 shows a DAC0830 operated with the output level shifted. The shift is made by summing a fixed current to the DAC current-output terminal, offsetting the output voltage to the op amp. The applied reference voltage then serves as the output-span controller and is added (in fractions) to the output as a function of the applied digital code. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 271, 1994, P. 665.   (View)

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Digital_potentiometer_with_composite_amplifier

Published:2009/7/25 5:26:00 Author:Jessie

Figure 9-32 shows a DAC1208 connected as a digital pot with improved characteristics (over those of the Fig. 9-31 circuit). The Fig. 9-32 circuit combines the excellent dc input characteristics of the classic LM11 with the fast response of a LF351 (a combination bipolar device). NANONAL SEMICONDUCTOR, APPLICATION NOTE 271, 1994, P. 665.   (View)

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74 Series digital circuit of 74152A, 74LS152 8-to-1 data selector

Published:2011/7/25 3:51:00 Author:Lucas | Keyword: 74 Series , digital circuit, 8-to-1 data selector

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Digital_potentiometer

Published:2009/7/25 5:25:00 Author:Jessie

Figure 9-31 shows a DAC0830 connected as a digital potentiometer (pot). The applied digital-input word multiplies the applied reference voltage. The resultant output voltage is the product of this multiplication, normalized to the resolution of the DAC. The op amp converts the DAC output current to a voltage through the 15-kΩ feedback resistor within the DAC. To preserve output linearity, the two current-output pins must be as close to 0 V as possible. Thus, the input-offset voltage of the op amp must be nulled. The amount of linearity-error degradation is about VOS + VREF When the digital pot is used to attenuate ac signals (in audio applications, for example), the DAC linearity over the full range of the applied reference voltage (even if it passes through zero) is good enough to distort a 10-V sine wave by only 0.004%. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 271, 1994, P. 665.   (View)

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Sine_wave_generator_with_digital_control

Published:2009/7/25 5:23:00 Author:Jessie

Figure 9-29 shows a DAC1020 connected to provide a variable-frequency, sine-wave generator. This circuit is capable of producing signals at frequencies up to 30 kHz under digital control. The linearity of the output frequency to the digital-code input is within 0.1% for each of the 1024 discrete output frequencies. To adjust the circuit, set all DAC digital inputs high and trim the 25-kΩ pot for a 30-kHz output (using a frequency counter). Then connect a distortion analyzer to the circuit output and adjust the 5-kΩ and 75-kΩ pots for minimum distortion. Finally, set the 1-MΩ output control for the desired output. The circuit provides rapid switching of the output frequency, as shown in Fig. 9-30. Notice that the output frequency shifts immediately (actually with no undesired delay) by more than an order of magnitude in response to digital commands (top line of Fig. 9-30). If operation over temperature is required, the absolute change in resistance in the DAC internal ladder might cause unacceptable errors. This can be corrected by reversing the A2 inputs and inserting an amplifier (dashed lines in Fig. 9-29) between the DAC and A1. Because this amplifier uses the DAC internal feedback resistor (Fig. 9-28), the temperature error in the ladder is cancelled. This results in more stable operation. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 269, 1994, P. 660.   (View)

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74 Series digital circuit of 74151A, 74LS151 8-to-1 data selector

Published:2011/7/25 3:52:00 Author:Lucas | Keyword: 74 Series, digital circuit , 8-to-1 data selector

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Multiplying_DACs

Published:2009/7/25 5:18:00 Author:Jessie

Figure 9-28 shows the internal functions of a multiplying DAC. Because Such four-quadrant DACs allow a digital word to operate on an analog input, or vice versa, the output can represent a sophisticated function. CMOS multiplying DACs allow true bipolar analog signals to be applied to the reference input. This feature makes such DACs useful in many applications that are not generally considered data converters. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 269, 1994, P. 659.   (View)

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Partially_decoded_6800_interface

Published:2009/7/25 5:17:00 Author:Jessie

Figure 9-27 shows the ADC0816/17 connected to form a partially decoded 6800 interface. This interface has more I/O-port strobes than the circuit of Fig. 9-26. A NAND gate and inverter are used to decode the addresses, VMA, and phase-2 clocki The I/O addresses are located at 11110XXXXXAABBBB (binary); where X = don't care; A = 00 (binary) for ALE write or IREQ reset/EOC read and A = 01 for START write or data read; and B channel-select address, if A, B, C, and D are connected to the address bus and ALE is accessed. A dual2-4 line decoder is used to generate these strobes. Inverters are used to create the correct logic levels. The 6800 supports only a wired-OR interrupt structure. In a multi-interrupt environment, only one interrupt is received and the interrupt-handler routine must determine which device has cause the interrupt and must service that device.To do this, the EOC is brought out to the data bus so that EOC can be checked by the CPU. NATIoNAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 610.   (View)

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Simple_6800_interface

Published:2009/7/25 5:15:00 Author:Jessie

Figure 9-26 shows the ADC0816/17 connected for a simple-or minimum 6800 interface. This circuit uses a DM8131 comparator to partically decode the A12, A13, A14, and A15 address lines with the phase-2 clock and VMA (valid memory address). This provides an address-decode pulse for the two NOT gates, which in turn generate the START/ALE pulse and the output-enable OE signal. Ihe design locates the ADC in one 4-kb or block. EOC is tied to IREQ interrupt through an inverter, and is usable only in single-interrupt systems because the 6800 has no way of resetting the interrupt (except by starting a new conversion). Because EOC is directly ties to the interrupt input, the controlling software must not re-enable interrupts until eight converter clock periods after the start pulse, when EOC is low. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 610.   (View)

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Minimum_NAC800_interface

Published:2009/7/25 5:13:00 Author:Jessie

Figure 9-25 shows the ADC0816/17 connected to form a simple or minimum NAC800 interface. This circuit uses NOR gates (similar to that of Fig. 9-20), but with different control signals. When EOC goes high, the flip-flop is set and INTR goes low. When the NSC800 acknowledges the interrupt by lowering INTA, the flip-flop resets. If more than one interrupt can occur simultaneously, either INTA should be gated with EOC, or a signal other than INTA must be used. This is required because the NSC800 can detect another interrupt and clear the ADC interrupt before the ADC signal is detected. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 609.   (View)

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