Published:2009/7/25 4:44:00 Author:Jessie | From:SeekIC
Figure 9-10 shows the ADC0816/17 connected to provide for 32-channel conversion. Such a configuration is possible because of the EC pin, which is actually a multiplexer enable. When the EC signal is low, all switches are inhibited so that another signal can be applied to the comparator input. Additional channels can be implemented as necessary. A total of five address lines are required to address the 32 channels. The lower four bits are applied directly to the A, B, C, and D inputs, All four bits are also applied to an MM74C174 flip-flop which is used as an address latch for the two CD4051s. The 1Q, 2Q, and 3Q outputs of the flip-flop feed the CD4051 address inputs. The 4Q and 5Q outputs are gated to form enable signals for each CD4051. Output 5Q is also applied at the EC input (after inversion) to enable the ADC multiplexer. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 596.
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