Partially_decoded_6800_interface

Published:2009/7/25 5:17:00 Author:Jessie | From:SeekIC

Figure 9-27 shows the ADC0816/17 connected to form a partially decoded 6800 interface. This interface has more I/O-port strobes than the circuit of Fig. 9-26. A NAND gate and inverter are used to decode the addresses, VMA, and phase-2 clocki The I/O addresses are located at 11110XXXXXAABBBB (binary); where X = don't care; A = 00 (binary) for ALE write or IREQ reset/EOC read and A = 01 for START write or data read; and B channel-select address, if A, B, C, and D are connected to the address bus and ALE is accessed. A dual2-4 line decoder is used to generate these strobes. Inverters are used to create the correct logic levels. The 6800 supports only a wired-OR interrupt structure. In a multi-interrupt environment, only one interrupt is received and the interrupt-handler routine must determine which device has cause the interrupt and must service that device.To do this, the EOC is brought out to the data bus so that EOC can be checked by the CPU. NATIoNAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 610.



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