Simple_6800_interface

Published:2009/7/25 5:15:00 Author:Jessie | From:SeekIC

Figure 9-26 shows the ADC0816/17 connected for a simple-or minimum 6800 interface. This circuit uses a DM8131 comparator to partically decode the A12, A13, A14, and A15 address lines with the phase-2 clock and VMA (valid memory address). This provides an address-decode pulse for the two NOT gates, which in turn generate the START/ALE pulse and the output-enable OE signal. Ihe design locates the ADC in one 4-kb or block. EOC is tied to IREQ interrupt through an inverter, and is usable only in single-interrupt systems because the 6800 has no way of resetting the interrupt (except by starting a new conversion). Because EOC is directly ties to the interrupt input, the controlling software must not re-enable interrupts until eight converter clock periods after the start pulse, when EOC is low. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 610.



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