W93900, W93902, W941232AD-5 Selling Leads, Datasheet
MFG:N/A Package Cooled:SSOP D/C:246
W93900, W93902, W941232AD-5 Datasheet download
Part Number: W93900
MFG: N/A
Package Cooled: SSOP
D/C: 246
W93900, W93902, W941232AD-5
- Table of contents:
Info of W93900
Info of W93902
Info of W941232AD-5
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About w9310
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Datasheet: w9310
File Size: 225532 KB
Manufacturer: Winbond
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About W93902
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Datasheet: W93902
File Size: 249876 KB
Manufacturer: Winbond
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About W941232AD
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Datasheet: W941232AD
File Size: 547910 KB
Manufacturer: Winbond
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W93902 General Description
The W93902 is a very-low-power decoder for pagers that is fully compatible with CCIR Radio Paging Code Number 1 (POCSAG code) operating at 512, 1200, or 2400 bps using a single 76.8 KHz crystal. To enhance the sensitivity of the pager system, a digital filter and digital PLL have been incorporated to remove the noise factor generated by the RF part and lock the signal phase.
To reduce the RF turn-on time and minimize power consumption, an advanced synchronization algorithm (1/18 turn on-time, as opposed to 1/17 or 1/16) is used to provide synchronization. Synchronization skip mode is also available for power reduction.
For convenient pager programming, the decoder provides fully software-programmable options and a simple CPU control format (data output packaged as 4/7/8 bits or not packaged). Also included are independent buzzer and LED frequency control outputs and a reference clock (32768 Hz, 64 Hz, 16 Hz, 1/60 Hz) that can be output or disabled. The decoder supports four independent user addresses, which can be assigned to different frames.
W93902 Features
· Data rate of 512, 1200, or 2400 bps
· 32768 Hz or 76800 Hz crystal
· Embedded digital filter and digital PLL
· Real two-random-bit error correction or one-bit error correction ability, plus four-bit burst error correction can be selected
· 1/18 RF enable time (more efficent than 1/17 or 1/16)
· Four real independent user address in different frames
· 25% to 75% duty cycle data capability in receive mode
· 2.7/3.2/2/4 KHz frequency output controlled by two pins, FBUZ1 and FBUZ2
· 6-bit/8-bit preamble acknowledge selection
· Four preamble search delay time settings
· Selection of from 1 to 15 sync search retry attempts
· Multi-frequency output for LED or other usage
· Inversion or non-inversion NRZIN signal and BS1/BS2/BS3 selection
· 4/7/8 bits package per byte output selection for receiving messages
· Independent power-saving control pin allows device to enter or exit reception mode at any time
· 16 selections for RF and PLL stable time
· Five selections for out-of-range indication
· Two selections for end-of-message condition
· Embedded power-on reset circuit
· Four Rxclk rate selection
· 2.5 to 5V operating voltage range
· Packaged in small size 24-pin SSOP
· 32768 Hz or 76800 Hz crystal
· Embedded digital filter and digital PLL
· Real two-random-bit error correction or one-bit error correction ability, plus four-bit burst error correction can be selected
· 1/18 RF enable time (more efficent than 1/17 or 1/16)
· Four real independent user address in different frames
· 25% to 75% duty cycle data capability in receive mode
· 2.7/3.2/2/4 KHz frequency output controlled by two pins, FBUZ1 and FBUZ2
· 6-bit/8-bit preamble acknowledge selection
· Four preamble search delay time settings
· Selection of from 1 to 15 sync search retry attempts
· Multi-frequency output for LED or other usage
· Inversion or non-inversion NRZIN signal and BS1/BS2/BS3 selection
· 4/7/8 bits package per byte output selection for receiving messages
· Independent power-saving control pin allows device to enter or exit reception mode at any time
· 16 selections for RF and PLL stable time
· Five selections for out-of-range indication
· Two selections for end-of-message condition
· Embedded power-on reset circuit
· Four Rxclk rate selection
· 2.5 to 5V operating voltage range
· Packaged in small size 24-pin SSOP
W93902 Connection Diagram
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