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W941232AD

Features: • 2.5V − 2.95V Power Supply• Double Data Rate architecture; two data transfers per clock cycle• Differential clock inputs (CLK and CLK )• DQS is edge-aligned with data for Read; center-aligned with data for Write• CAS Latency: 3 and 4• Burst Leng...

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SeekIC No. : 004545330 Detail

W941232AD: Features: • 2.5V − 2.95V Power Supply• Double Data Rate architecture; two data transfers per clock cycle• Differential clock inputs (CLK and CLK )• DQS is edge-aligned ...

W941232AD Data Sheet

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Part Number:
W941232AD
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 2.5V − 2.95V Power Supply
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and CLK )
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 3 and 4
• Burst Length: 2, 4 and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power Down
• Write Data Mask
• Write Latency = 1
• 4K Refresh cycles / 64 mS
• Interface: SSTL-2
• Packaged in LQFP 100-pin, 630 x 866 mil, 0.65 mm pin pitch


Pinout

Connection Diagram


Specifications

SYMBOL
 PARAMETER
RATING
UNIT
NOTES
VIN
 Input Voltage Relative to Vss
-0.3 − VDD +0.3
V
1
VOUT
 Output Voltage Relative to Vss
-0.3 − VDDQ +0.3
V
1
VDD
 Power Supply Voltage Relative to Vss
-0.3 − 3.6
V
1
VDDQ
 I/O Power Supply Voltage relative to Vss
-0.3 − 3.6
V
1
TOPR
 Operating Temperature
0 − 70
°C
1
TSTG
 Storage Temperature
-55 − 150
°C
1
TSOLDER
 Soldering Temperature (10s)
260
°C
1
PD
 Power Dissipation
1
W
1
IOUT
 Short Circuit Output Current
50
mA
1



Description

W941232AD is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 1,048,576 words * 4 banks * 32 bits. Using pipelined architecture and 0.175 m process technology, W941232AD delivers a data bandwidth of up to 800M words per second (-5). For different application, W941232AD was sorted into the following speed grades: -5. The -5 parts can run up to 200 MHz/CL3.

All inputs of W941232AD reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W941232AD is ideal for main memory in high performance applications.




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