W942508BH

W942508BH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 8,388,608 words ´ 4 banks ´ 8 bits. Using pipelined architecture and 0.175 mm process technology, W942508BH delivers a data bandwidth of up to 286M words per second (-7). To fully comply with the personal computer industrial standard, W942508BH is sorted into three speed grades: -7, -75 The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification.

All Inputs of W942508BH reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942508BH is ideal for main memory in high performance applications.