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W942516BH

Features: · 2.5V ±0.2V Power Supply· Up to 143 MHz Clock Frequency· Double Data Rate architecture; two data transfers per clock cycle· Differential clock inputs (CLK andCLK )· DQS is edge-aligned with data for Read; center-aligned with data for Write· CAS Latency: 2 and 2.5· Burst Length: 2, 4 and...

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SeekIC No. : 004545334 Detail

W942516BH: Features: · 2.5V ±0.2V Power Supply· Up to 143 MHz Clock Frequency· Double Data Rate architecture; two data transfers per clock cycle· Differential clock inputs (CLK andCLK )· DQS is edge-aligned wi...

W942516BH Data Sheet

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Part Number:
W942516BH
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· 2.5V ±0.2V Power Supply
· Up to 143 MHz Clock Frequency
· Double Data Rate architecture; two data transfers per clock cycle
· Differential clock inputs (CLK andCLK )
· DQS is edge-aligned with data for Read; center-aligned with data for Write
· CAS Latency: 2 and 2.5
· Burst Length: 2, 4 and 8
· Auto Refresh and Self Refresh
· Precharged Power Down and Active Power Down
· Write Data Mask
· Write Latency = 1
· 8K Refresh Cycles / 64 mS
· Interface: SSTL-2
· Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65 mm pin pitch


Pinout

Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
Input/Output Voltage
VIN, VOUT
-0.3 − VDDQ +0.3
V
Power Supply Voltage
VDD, VDDQ
-0.3 − 3.6
V
Operating Temperature
TOPR
0 - 70
°C
Storage Temperature
TSTG
-55 - 150
°C
Soldering Temperature (10s)
TSOLDER
260
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.


Description

W942516BH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words ´ 4 banks ´ 16 bits. Using pipelined architecture and 0.175 mm process technology, W942516BH delivers a data bandwidth of up to 286M words per second (-7). To fully comply with the personal computer industrial standard, W942516BH is sorted into three speed grades: -7, -75 and The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification.

All Inputs of W942516BH reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942516BH is ideal for main memory in high performance applications.




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