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PCK2014, PCK2022, PCK2057

Table of contents:
Info of PCK2014
Info of PCK2022
Info of PCK2057

PCK2014, PCK2022, PCK2057 Selling Leads, Datasheet

MFG:PHI Package Cooled:SSOP D/C:00+

PCK2014, PCK2022, PCK2057 Datasheet download

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Part Number: PCK2014

MFG: PHI

Package Cooled: SSOP

D/C: 00+

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PCK2057 General Description

The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN,FBIN ), the 2-line serial interface (SDA, SCL), and the analog power input (AVDD). The two-line serial interface (I2C) can put the individual output clock pairs in a high-impedance state. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The device provides a standard mode (100 kbits) I2C interface for device control. The implementation is as a slave/receiver. The serial inputs (SDA, SCL) provide integrated pull-up resistors (typically 100 kW).

Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at power-up. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers is not supported). The I2C interface circuit can be supplied with either 2.5 V or 3.3 V (VDDI2C).

Since the PCK2057 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power-up.

PCK2057 Maximum Ratings

SYMBOL	PARAMETER		CONDITION	LIMITS		UNIT
SYMBOL	PARAMETER		CONDITION	MIN	MAX	UNIT
V_DDQ/A_VDD	Supply voltage range			0.5	3.6	V
VDDI²_C	I²C supply voltage range			0.5	3.6	V
V_I	Input voltage range	except SCL and SDA	see Notes 2 and 3	0.5	V_DDQ + 0.5	V
V_I	Input voltage range	SCL and SDA	see Notes 2 and 3	0.5	VDDI²_C + 0.5	V
V_O	Output voltage range		see Notes 2 and 3	-0.5	V_DDQ + 0.5	V
I_IK	Input clamp current		VI < 0 or VI >V_DDQ	-	±50	mA
I_OK	Output clamp current		VO < 0 or VO >V_DDQ	-	±50	mA
I_O	Continuous output current		VO = 0 to V_DDQ		±50	mA
	Continuous current to GND or V_DDQ			-	±100	mA
P_tot	Storage temperature range			-65	+150	°C

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. This value is limited to 3.6 V maximum.

PCK2057 Features

• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications supporting DDR 200/266/300/333
• Full DDR solution provided when used with PCK2002P or PCK2002PL, and PCK2022RA
• 1-to-10 differential clock distribution
• Very low jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
• SSTL_2 interface clock inputs and outputs
• HCSL to SSTL_2 input conversion
• Test mode enables buffers while disabling PLL
• Tolerant of Spread Spectrum input clock
• 3.3 V I2C support with 3.3 V VDDI2C
• 2.5 V I2C support with 2.5 V VDDI2C
• Form, fit, and function compatible with CDCV850

PCK2057 Connection Diagram

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