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These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
NDC632P Maximum Ratings
Symbol
Parameter
NDC632P
Units
VDSS VGSS
Drain-Source Voltage Gate-Source Voltage - Continuous
·-2.7A, -20V. RDS(ON) = 0.14W @ VGS = -4.5V RDS(ON) = 0.2W @ VGS = -2.7V. ·Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. ·High density cell design for extremely low RDS(ON). ·Exceptional on-resistance and maximum DC current capability.