MTB23P06E, MTB23P06V, MTB23P06V/D Selling Leads, Datasheet
MFG:MOT Package Cooled:. D/C:TO
MTB23P06E, MTB23P06V, MTB23P06V/D Datasheet download
Part Number: MTB23P06E
MFG: MOT
Package Cooled: .
D/C: TO
MFG:MOT Package Cooled:. D/C:TO
MTB23P06E, MTB23P06V, MTB23P06V/D Datasheet download
MFG: MOT
Package Cooled: .
D/C: TO
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Datasheet: MTB23P06E
File Size: 287291 KB
Manufacturer: MOTOROLA [Motorola, Inc]
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Datasheet: MTB23P06V
File Size: 255086 KB
Manufacturer: MOTOROLA [Motorola, Inc]
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Datasheet: MTB23P06V/D
File Size: 222748 KB
Manufacturer:
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The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced TMOS EFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
Rating |
Symbol |
Value |
Unit |
DraintoSource Voltage |
VDSS |
60 |
Vdc |
DraintoGate Voltage (RGS = 1.0 M) |
VDGR |
60 |
Vdc |
GatetoSource Voltage - Continuous |
VGS |
±20 |
Vdc |
Drain Current - Continuous - Continuous @ 100 - Single Pulse (tp 10 s) |
ID ID IDM |
23 14 75 |
Adc Apk |
Total Power Dissipation @ 25 Derate above 25 Total Power Dissipation @ TA = 25 (1) |
PD |
125 1.0 2.5 |
Watts W/ Watts |
Operating and Storage Temperature Range |
TJ, Tstg |
55 to 150 |
|
Single Pulse DraintoSource Avalanche Energy - Starting TJ = 25 (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 23 Apk, L = 5.7 mH, RG = 25 ) |
EAS |
1500 |
mJ |
Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (1) |
RJC RJA RJA |
1.0 62.5 50 |
/W |
Maximum Lead Temperature for Soldering Purposes, 1/8"from case for 10 seconds |
TL |
260 |
Designer's Data for "Worst Case" Conditions - The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves - representing boundaries on device characteristics - are given to facilitate "worst case" design.
EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company
TMOS V is a new technology designed to achieve an onresistance area product about onehalf that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS EFET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
Rating |
Symbol |
Value |
Unit |
DraintoSource Voltage |
VDSS |
60 |
Vdc |
DraintoGate Voltage (RGS = 1.0 M) |
VDGR |
60 |
Vdc |
GatetoSource Voltage - Continuous - NonRepetitive (tp 10 ms) |
VGS VGSM |
± 15 ± 25 |
Vdc Vpk |
Drain Current - Continuous - Continuous @ 100 - Single Pulse (tp 10 s) |
ID ID IDM |
23 15 81 |
Adc Apk |
Total Power Dissipation @ 25 Derate above 25 Total Power Dissipation @ TA = 25 (1) |
PD |
90 0.60 3.0 |
Watts W/ Watts |
Operating and Storage Temperature Range |
TJ, Tstg |
55 to 175 |
|
Single Pulse DraintoSource Avalanche Energy - STARTING TJ = 25 (VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25 ) |
EAS |
794 |
mJ |
Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (1) |
RJC RJA RJA |
1.67 62.5 50 |
/W |
Maximum Lead Temperature for Soldering Purposes, 1/8"from case for 10 seconds |
TL |
260 |
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer's Data for "Worst Case" Conditions - The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves - representing boundaries on device characteristics - are given to facilitate "worst case" design.
EFET, Designer's and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.