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FDV302N, FDV302P, FDV302P-NL

Table of contents:
Info of FDV302N
Info of FDV302P
Info of FDV302P-NL

FDV302N, FDV302P, FDV302P-NL Selling Leads, Datasheet

MFG:Fairchild Semiconductor Category:Discrete Semiconductor Products Package Cooled:SOT23-3 D/C:.

FDV302N, FDV302P, FDV302P-NL Datasheet download

Five Points

Part Number: FDV302P

Category: Discrete Semiconductor Products

MFG: Fairchild Semiconductor

Package Cooled: SOT23-3

D/C: .

Description: MOSFET P-CH 25V 120MA SOT-23

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FDV302P Parameters

Technical/Catalog Information	FDV302P
Vendor	Fairchild Semiconductor
Category	Discrete Semiconductor Products
Mounting Type	Surface Mount
FET Polarity	P-Channel
Drain to Source Voltage (Vdss)	25V
Current - Continuous Drain (Id) @ 25° C	120mA
Rds On (Max) @ Id, Vgs	10 Ohm @ 200mA, 4.5V
Input Capacitance (Ciss) @ Vds	11pF @ 10V
Power - Max	350mW
Packaging	Tape & Reel (TR)
Gate Charge (Qg) @ Vgs	0.31nC @ 4.5V
Package / Case	SOT-23
FET Feature	Standard
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	FDV302P FDV302P FDV302PTR ND FDV302PTRND FDV302PTR

FDV302P General Description

This P-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.

FDV302P Maximum Ratings

Symbol	Parameter	FDV302P	Units
V_DSS	Drain-Source Voltage	-25	V
V_GSS	Gate-Source Voltage	-8	V
I_D	Drain Current - Continuous - Pulsed	-0.12	A
I_D	Drain Current - Continuous - Pulsed	-0.5	A
P_D	Maximum Power Dissipation	0.35	W
T_J,T_STG	Operating and Storage Temperature Range	-55 to 150	°C
E_SD	Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm)	6.0	kV

FDV302P Features

-25 V, -0.12 A continuous, -0.5 A Peak.

R_DS(ON) = 13@ V_GS= -2.7 V

R_DS(ON) = 10@ V_GS= -4.5 V

Very low level gate drive requirements allowing direct operation in 3V circuits. V_GS(th) < 1.5V.

Gate-Source Zener for ESD ruggedness.>6kV Human Body Model

Compact industry standard SOT-23 surface mount package.

Replace many PNP digital transistors (DTCx and DCDx) with one DMOS FET.

FDV302P Connection Diagram

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