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This N-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one N-channel FET can replace several different digital transistors, with different bias resistor values.
FDV301N Maximum Ratings
Symbol
Parameter
FDV301N
Units
VDSS , VCC
Drain-Source Voltage, Power Supply Voltage
25
V
VGSS , VI
Gate-Source Voltage, VIN
8
V
ID , IO
Drain/Output Current - Continuous
0.22
A
0.5
PD
Maximum Power Dissipation
0.35
W
TJ,TSTG
Operating and Storage Temperature Range
-55 to 150
°C
ESD
Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm)
6.0
kV
FDV301N Features
25 V, 0.22 A continuous, 0.5 A Peak. RDS(ON) = 5 @ VGS = 2.7 V RDS(ON) = 4 @ VGS = 4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace multiple NPN digital transistors with one DMOS FET.