CMOS_A_D_converter_with_complementary_logic_0_V_to__VSUBREF_SUB_input

Published:2009/7/22 22:34:00 Author:Jessie

The ADC used in this circuit combines the SAR, the DAC and the comparator in a single IC. Compare this to the A/D of Fig. 6-43.   (View)

View full Circuit Diagram | Comments | Reading(504)

DIGITIZING_POT_POSITION

Published:2009/7/6 20:32:00 Author:May

Converts position of pot arm into digital value, using NE555 timer and several bytes of program in 8008 or 8080 microprocessor having 2.5-μs clock. NE555 is triggered at pin 2 by 0UT TRIGGER instruction. Program monitors output at pin 3 in loop that increments B register. When NE555 times out, program exits from subroutine and B register contains digital representation of pot position.-J. M. Schulein, Pot Position Digitizing Idea, BYTE, March 1976, p 79.   (View)

View full Circuit Diagram | Comments | Reading(1021)

MUSIC_ON_HOLD

Published:2009/7/6 20:29:00 Author:May

With this music-on-hold device, you can answer the phone in one room, place the caller on hold, and then pick up the phone again at another location. When you pick up the phone the second time, you automatically deactivate the music-on-hold feature and can continue your conversation.   (View)

View full Circuit Diagram | Comments | Reading(1792)

SLOW_STEPPER

Published:2009/7/6 20:28:00 Author:May

Addition of slow-stepping switch position to single-step circuit of micro.processor eliminates need for pushing single step switch repeatedly while executing endless loop program and watching address and data lights to see where program or hardware fails during debugging run. Circuit uses 74123 mono MVBR to give 1,5-ms pulses on single step and 150-ms on slow step.-H. R. Bendrot, The Slow-Stepping Debugger, Kilobaud, April 1977, p 60.   (View)

View full Circuit Diagram | Comments | Reading(1065)

LIGHT_PEN

Published:2009/7/6 20:26:00 Author:May

Photocell in tip of light pen senses when dot is written on screen at its location by becoming conductive and biasing al so it feeds short pulse through 01 to base of 02. If pulse is greater than 0.6V, Q2 is driven into saturation and output of pen drops to 0.3 V. Output line goes to pin 5 of digital display unit (DDU), which writes 1 or 0 (dot or no dot! on screen at instant that electron beam of CRT terminal reaches position of pen. Sensitivity control can be adjusted so illuminated dot just ahead of pen can be used to create new dot in adjacent dark space. If screen is dark all around pen, footswitch-con-trolled auxiliary circuit can be used to override Z-axis control and flood screen with light momentarily by feeding logic 1 to2 input. This mode can be used for creating or correcting graphics.-S. S. Loomis, Let There Be Light Pens, BYTE, Jan, 1976, p 26-30.   (View)

View full Circuit Diagram | Comments | Reading(909)

MUSICAL_TELEPHONE_RINGER

Published:2009/7/6 20:24:00 Author:May

The heart of the circuit is IC1, General Instrument's AY-3-1350 melody-synthesizer IC. IC2 is a TCM1512 telephone ring detector IC that is powered by the telephone line. The circuit's operation begins when IC2 senses a ring pulse on the telephone line. The detector (internally) rectifies the ring signal and then outputs a voltage to relay RY1 (an SPST reed-type relay with 5 volt contacts), causing its contacts to close. That pulls pin 12 (the ON/OFF control) of IC1 low (logic 0 ), causing it to output a signal-the selected tune-to transistor amplifier Q2. The amplified signal is then fed to the speaker. The melody continues to play either until the tune is finished (at which time IC1 returns to the standby mode), or until someone takes the phone off the hook. Taking the phone off the hook dis-continues the ring pulses to IC2, which opens RY1. When the relay contacts open, pin 12 of IC1 goes high, returning the circuit to the standby mode to wait for the next incoming phone call.   (View)

View full Circuit Diagram | Comments | Reading(3324)

TERMINAL_INTERFACE

Published:2009/7/6 20:22:00 Author:May

Developed for use between computer terminal and microprocessor development board. Provides interface between teleprinter terminal using EIA RS-2320 standard and input of microcomputer (upper diagram) and interface bemoan computer and teleprinter using 20-mA current-loop standard for actuating printout. Logic 1 is -3 to -9 V or less, and logic 0 is +3 to +9 V or more.-P. Snigier, Constructing a Low-Cost Terminal Inter-face, EDN Magazine, June 5, 1977, p 205-206.   (View)

View full Circuit Diagram | Comments | Reading(606)

SINGLE_CHIP_FREQUENCY_DOUBLER

Published:2009/7/6 20:21:00 Author:May

The frequency doubler uses only one IC. Like other doublers, this circuit uses both the rising and falling edges of the input signals to produce digital pulses, thus effectively doubling the input's frequency.Without the rc networks at IC1 inputs, IC1 would not produce any output pulses. However, the rc networks delay one edge with respect to the other. The A input lags the B input for positive-going edges, and the B input lags the A input for negative-going ones. You can vary the output duty cycle from 0 to 100% by varying R3. IC1's minimum output pulse width defines the maximum frequency of this circuit.   (View)

View full Circuit Diagram | Comments | Reading(1596)

SCRAMBLE_PHONE

Published:2009/7/6 20:21:00 Author:May

IC-1 and the associated circuitry form a stable audio tone generator that feeds a buffer amplifier, Q1 and Q2. The tone output is taken from the emitters of the transistor pair to supply a carrier voltage for a balanced modulator made up of four diodes-Dl through D4-and T1 and T2. If the two transformers and the four diodes are perfectly matched (which is almost impossible to achieve and not necessary in any case) no carrier will appear at the input or output of T1 or T2. In a practical circuit, a small amount of unbalance will occur and produce a low-level carrier tone at the input and output of the balanced modulator. A telephone carbon mike and earpiece are connected to the low impedance winding of T1, with a three volt battery supplying the necessary mike current.Trim potentiometer R4 is used to make a fine frequency adjustment of the oscillator so that two scrambler units may be synchronized to the same carrier frequency. Rg limits,line current to 25 mA.   (View)

View full Circuit Diagram | Comments | Reading(711)

ODD_NUMBER_COUNTER_DIVIDER

Published:2009/7/6 20:20:00 Author:May

This circuit, shown symmetrically, divides an input by virtually any odd number. The circuit counts n + 1/2 clocks twice to achieve the desired divisor. By selecting the proper n, which is the decoded output of the LS161 counter, you can obtain divisors front 3 to 31. The circuit, as shown, divides by 25; you can obtain higher divisors by cascading additional LS161 counters. The counter and IC5A form the n + 1/2 counter. Once the counter reaches the decoded count, n, IC5A ticks off an additional 1/2 clock, which clears the counter and puts it in hold. Additionally, IC5A clocks IC5B, which changes the clock phasing through the XOR gate, IC1. The next edge of the input clocks IC5A, which reenables the counter to start counting for an additional n + 1/2 cycles. Although the circuit has been tested at 16 MHz, a worst-case timing analysis reveals that the maximum input frequency is between 7 and 8 MHz.   (View)

View full Circuit Diagram | Comments | Reading(831)

SPEECH_ACTIVITY_DETECTOR_FOR_TELEPHONE_LINES

Published:2009/7/6 20:19:00 Author:May

The circuit can be used in telephone lines for speech activity detection purposes.This detection is very useful in the case of half-duplex conversation between two stations, in the case of simultaneous transmission of voice and data over the same pair of cables by the method of interspersion data on voice traffic, and also in echo suppressor devices.The circuit consists of a class-A amplifier in order to amplify the weak analog signals (in the range 25-2100 mW of an analog telephone line).The IC1 is connected as a retriggerable monostable multivibrator with the Tr2 discharging the timing capacitor C3, if the pulse train reaches the trigger input 2 of IC1 with period less than the time: Thigh=1.1 (R3 C3) The output 3 of IC1 is active ON when an analog or digital signal is presented at the output and it drops to low level, Thigh seconds after the input signal has ceased to exist.   (View)

View full Circuit Diagram | Comments | Reading(638)

DIVIDE_BY_1_1_2_CIRCUIT

Published:2009/7/6 20:18:00 Author:May

An input signal drives both SN7474 D-type flip-flops, which are positive edge-triggered devices. A low-to-high input signal transition triggers the A flip-flop, while a high-to-low input signal transition triggers the B flip-flop via the SN7404 inverter. Either flip-flop in the high state will cause the output to decrease via the SN7402 NOR gate. This in turn disables the opposite flip-flop from going to the high state. The flip-flop in the high state remains there for one clock period, then it is clocked low. With both flip-flops low, the output increases, enabling the opposite flip-flop to be clocked high one-half clock cycle later. This alternate enabling and disabling action of the flip-flops results in a divide-by-1 1/2 function. That is, three clock pulses in, produce two evenly spaced clock pulses out. The circuit has no lock-up states and no inherent glitches. Replacing the NOR gate with an SN7400 NAND gate inverts the A, B, and output signals. By adding sim-ple binary or BCD counters, counting chains, such as divide-by-3, -6, -12, -24, -15, -30, etc., can be gen-erated using the divide-by-1 1/2 circuit as a basis.   (View)

View full Circuit Diagram | Comments | Reading(2589)

POT_INTERFACE

Published:2009/7/6 20:18:00 Author:May

Circuit converts resistance of pot setting to frequency with NE555 timer IC1.Frequency is measured under direct control of microprocessor program, using 8-bit counter with CPU clock as time base. Processor is programmed to clear counter, turn on counter, wait 2 ms, turn off counter, and read count. Result is number of cycles in 2-ms period, ranging from 1 to about 240. Relationship of frequency to control position is accurate enough for game control. R1, R2, R3, and 01 are chosen so frequency varies from about 0.75 to 122 kHz as Ra is varied from 100K to 0. Use audio-taper pot to improve conversion linearity. Article gives subroutines for Motorola 6800 and Intel 8080 microprocessors.-C. Helmers, Getting Inputs from Joy-sticks and Slide Pots, BYTE, Feb. 1976, p 86-88.   (View)

View full Circuit Diagram | Comments | Reading(1832)

TAPE_RECORDER_POSITION_INDICATOR_CONTROLLER

Published:2009/7/6 20:16:00 Author:May

This circuit is representative of the many applications of up/down counting in monitoring dimensional position. In the tape recorder application, the LOAD REGIS-TER, EQUAL, and ZERO outputs are used to control the recorder. To make the recorder stop at a particular point on the tape, the register can be set with the stop at a particular point on the tape, the register can be set with the stop point and the EQUAL output used to stop the recorder either on fast forward, play or rewind.To make the recorder stop before the tape comes free of the reel on rewind, a leader should be used. Resetting the counter at the starting point of the tape, a few feet from the end of the leader, allows the ZER0 output to be used to stop the recorder on rewind, leaving the leader on the reel. The 1 M ohm resistor and.0047 μF capacitor on the COUNT INPUT provide a time constant of about 5 ms to debounce the reel switch.The Schmitt trigger on the COUNT INPUT of the ICM7217 squares up the signal before applying it to the counter. This technique may be used to debounce switchclosure inputs in other applications.   (View)

View full Circuit Diagram | Comments | Reading(586)

DIGITAL_FREQUENCY_DOUBLER

Published:2009/7/6 20:15:00 Author:May

The circuit doubles the frequency of a digital signal by operating on both signal edges. Each transition causes exclusive-OR gate IC1 to produce a pulse, which clocks flip-flop IC3 after propagating through buffers IC2C and IC2B. If you remove capacitor C1, the circuit produces narrow output pulses. By including C1, you can obtain a desired duty cycle for a given input frequency flN. The C1 value for an approximate 50% dutycycle is:   (View)

View full Circuit Diagram | Comments | Reading(1375)

PCF8596 Microcomputer and Auxiliary Function Integrated Circuit

Published:2011/7/29 0:01:00 Author:Michel | Keyword: Microcomputer, Auxiliary Function, Integrated Circuit

PCF8596 is PCF8596 microcomputer and the auxiliary function integrated circuit produced by Philips Company and it is widely used in ChangHong series color TVs. First,Functions Features Inside Assitant Circuit of PCF8596 Integrated CircuitPCF859 IC adopts 8 feet DIP package and its pins functions and data are shown as table 1 and the data is measured from ChangHong CN-15 big screen color TV. Table 1:PCF8596 IC Pins Fuctions and Data   (View)

View full Circuit Diagram | Comments | Reading(646)

TAPE_RECORDER_INTERFACE

Published:2009/7/6 20:12:00 Author:May

The interface allows data to be saved on an ordinary tape recorder at a speed of 2400 bit/s.The serial stream of data Fig. 1 (A) is coded with a clock of 2400 Hz (B), by means of XOR gate IC 1/1. Logical high and low appear as shown in Fig. 2 (C). These impulses are lowered in amplitude and feed into the record input of a low cost tape recorder.During the playback, pulses (D) are amplified with CMOS gate IC 1/2 connected as a linear amplifier, and providing a TTL level signal shown in (E). On both positive and negative transitions IC 1/4 forms short pulses as shown in (F) (approx. 50 ps) that triggers one shot IC2. A monostable one shot pulse width is adjusted to be 3/4 of bit length (310 pts). A change from high to low in a coded stream generates a low pulse width of one bit cell. The same is for change from low to high that generates a high pulse of the same width. During this pulse one shot latches the state of line E in D type flip-flop IC3 (G). When a stream consists of multiple ones or zeros, the one shot is retriggered before it comes to the end of the quasistable state and the state of the flip-flop remains unchanged. The original data stream is available at the output of the flip-flop (H). 280 the DUART that receives these pulses is programmed so that the receiver clock is 16 times the data rate (38.4 kHz).   (View)

View full Circuit Diagram | Comments | Reading(746)

SAFETY_FLARE

Published:2009/7/6 20:04:00 Author:May

When 51 is on, power is applied to an oscillator composed of Q1, R1, C1, L1, and L2. Coil L1 is the primary winding of T1, and L2 is the feedback winding. When Q1 turns on, its collector current saturates T1's ferrite core. That, in turn, removes the base drive to Q1 through L2. Transistor Q1 then turns off. As the field around L1 and L2 decays, Q1 will eventually turn on again, and the cycle repeats over, and over.Transformer T1 is a step-up, ferritecore, potted-type unit whose secondary;winding (L3) output is rectified by D2 and filtered by C2. That capacitor charges up to around 250 to 300 volts, which is applied to the resistor divider composed of R3 and R4, along with the flash tube FX1.Capacitors C3 and C4 will charge up to around 200 and 100 volts, through R3 and R4, respectively. Flash rate is adjustable via R4. When the charge on C4 gets to around 100 volts, neon lamp NE1 fires discharging C4 into the gate circuit of silicon control rectifier SCR1. The SCR1 turns on discharging C3 into the primary winding of trigger-pulse transformer T2, Transformer T2 is another step-up, pulse-type unit providing an output of around 4 kW across transformer T2's secondary winding.The xenon gas inside FX1 is ionized and a bright flash is emitted. Finally, C3 quickly discharges through L4, and the cycle repeats over, and over.   (View)

View full Circuit Diagram | Comments | Reading(669)

SIMPLE_STROBE

Published:2009/7/6 20:03:00 Author:May

Initially the neon and xenon lamps are not conducting and act like a very high (almost infinite) resistance. Capacitors C1 and C4 in conjunction with D1 and D2 form a voltage doubler circuit, which can charge C2 up to about 300 Vdc after several ac cycles.Voltage increases as current is supplied through R1 and R2. Neon bulb I1 will all of a sudden start to conduct when the voltage across C3 reaches 11's ionization potential.While conducting, the resistance of the bulb will be relative low. Due to this sudden conduction, a pulse of current will pass through the primary of T1. The turns ratio is such that about 400 V will be developed at the secondary. The xenon tube is similar to the neon bulb in that it produces light when the gas ionizes and conducts. However, it is designed so that an external signal (the 4 kV on the metal ring around the tube) ionizes the gas and initiates the conduction. When F1 conducts, it discharges C2. At this point, the whole cycle starts over again. The purpose of R2 is to vary the rate at which C3 charges, and hence the repetition rate of the strobe.   (View)

View full Circuit Diagram | Comments | Reading(974)

FREQUENCY_DOUBLER

Published:2009/7/6 9:38:00 Author:May

The output contains the sum component, which is twice the frequency of the input, since both input signals are the same frequency.   (View)

View full Circuit Diagram | Comments | Reading(0)

Pages:254/471 At 20241242243244245246247248249250251252253254255256257258259260Under 20