MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:QFP D/C:2008
TSB12LV01B, TSB12LV01BPZT, TSB12LV21APGF Datasheet download
Category: Integrated Circuits (ICs)
MFG: Texas Instruments
Package Cooled: QFP
D/C: 2008
Description: IC HP 3.3V LINK LAYER 100-TQFP
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Datasheet: TSB12LV01B
File Size: 429029 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TSB12LV01BPZT
File Size: 448891 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TSB12LV21APGF
File Size: 264940 KB
Manufacturer: TI [Texas Instruments]
Download : Click here to Download
The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).
• Two new internal registers have been added at CFR address 40h and 44h. The Host Bus Control Register at 40h and the Mux Control Register @44h are described in section 3.2.
• Three programmable general-purpose output pins have been added. A detailed description is provided in section 1.3.
• Several pin changes have been made. Refer to TSB12LV01A to TSB12LV01B Transition Document, TI literature number SLLA081 dated May 2000.
However, there are three restrictions that were not present in the TSB12LV01A device: • The TSB12LV01B may only operate with a 50 MHz host-interface clock (BCLK) if the duty cycle is less than 5% away from the 50-50 point, (i.e., the duty cycle must be within 45-55% inclusive). A 40-60% duty cycle clock is acceptable for host clock frequencies at or below 47 MHz.
• The TSB12LV01B does not have bus holder cells on the PHY-link interface.
• As a result of removing the bus holder cells, the ISO pin (pin 69) was replaced with a Vcc pin on the TSB12LV01B.
| Technical/Catalog Information | TSB12LV01BPZT |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Controller Type | Link Layer Controller |
| Interface | IEEE 1394 |
| Voltage - Supply | 3.3V, 5V |
| Current - Supply | - |
| Package / Case | 100-TQFP |
| Packaging | Tray |
| Operating Temperature | - |
| Drawing Number | 296; 4073179; PZT; 100 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | TSB12LV01BPZT TSB12LV01BPZT 296 11062 ND 29611062ND 296-11062 |
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