TSB11LV01

· Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus†
· Fully Interoperable With FireWireE Implementation of IEEE 1394-1995
· Provides A Single Fully-Compliant Cable Port at 100 Megabits per Second (Mbits/s)
· Cable Port Monitors Line Conditions for Active Connection to a Remote Node
· Inactive Port Disabled to Save Power
· Cable Inactivity Monitor Output and Power-down Input Provided for Additional Sleep-Mode Power Savings
· Internal Bandgap Reference Provided for Setting Stable Operating Bias Conditions
· Logic Performs System Initialization and Arbitration Functions
· Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding
· Incoming Data Resynchronized to Local Clock
· Data Interface to Link Layer Controller (Link) Provided Through Two Parallel Signal Lines at 50 Mbits/s
· 25-MHz Crystal Oscillator and PLL Provide Transmit, Receive Data, and Link Layer Controller Clocks at 50 MHz
· Digital I/Os are 5 V tolerant
· Node Power Class Information Signaling for System Power Management
· Cable Power Presence Monitoring
· Cable Bias and Driver Termination Voltage Supply
· Single 3-V Supply Operation
· Separate Multiple Package Terminals Provided for Analog and Digital Supplies and Grounds
· High Performance 48-Pin TQFP (PT) Package

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . .  See Dissipation Rating Table
Operating free air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . .   65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

The TSB11LV01 provides the analog transceiver functions needed to implement a single port node in a cable based IEEE 1394-1995 network. The cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB11LV01 is designed to interface with a link layer controller, such as the TSB12C01A.

The TSB11LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL) generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided to provide the 49.152-MHz ±100 ppm system clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link for synchronization of the two chips and is used for resynchronization of the received data. The power-down function, when enabled by asserting the PWRDN terminal high, stops operation of the PLL.

Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the TSB11LV01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304-Mbits/s as the outbound data-strobe information stream. During transmit, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair.