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These logic level N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
NDB6060L Maximum Ratings
Symbol
Parameter
NDP6060L
NDB6060L
Units
VDSS
Drain-Source Voltage
60
V
VDGR
Drain-Gate Voltage (RGS < 1 MW)
60
V
VDSS
Gate-Source Voltage - Continuous - Nonrepetitive (tP < 50 µs)
± 16
V
± 25
ID
Drain Current - Continuous - Pulsed
48
A
144
PD
Total Power Dissipation @ TC = 25°C Derate above 25°C
100
W
0.67
W/
TJ,TSTG
Operating and Storage Temperature
-65 to 175
TL
Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
275
NDB6060L Features
`48A, 60V. RDS(ON) = 0.025 @ VGS = 5V. `Low drive requirements allowing operation directly from logic drivers. VGS(TH) < 2.0V. `Critical DC electrical parameters specified at elevated temperature. `Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. `175°C maximum junction temperature rating. `High density cell design for extremely low RDS(ON). `TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.