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M2V56S40TP, M2V56S40TP6, M2V56S40TP-6

Table of contents:
Info of M2V56S40TP
Info of M2V56S40TP6
Info of M2V56S40TP-6

M2V56S40TP, M2V56S40TP6, M2V56S40TP-6 Selling Leads, Datasheet

Package Cooled:TSOP D/C:TSOP

M2V56S40TP, M2V56S40TP6, M2V56S40TP-6 Picture

M2V56S40TP, M2V56S40TP6, M2V56S40TP-6 Datasheet download

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Part Number: M2V56S40TP

MFG: --

Package Cooled: TSOP

D/C: TSOP

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M2V56S40TP General Description

M2V56S20TP is a 4-bank x 16777216-word x 4-bit, 2V56S30TP is a 4-bank x 8388608-word x 8-bit, 2V56S40TP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz (-6), and are suitable for main memory or graphic memory in computer systems.

M2V56S40TP Maximum Ratings

Symbol	Parameter	Conditions	Ratings	Unit
Vdd	Supply Voltage	with respect to Vss	-0.5 ~ 4.6	V
VddQ	Supply Voltage for Output	with respect to VssQ	-0.5 ~ 4.6	V
VI	Input Voltage	with respect to Vss	-0.5 ~ Vdd+0.5	V
VO	Output Voltage	with respect to VssQ	-0.5~ VddQ+0.5	V
IO	Output Current		50	mA
Pd	Power Dissipation	Ta = 25	1000	mW
Topr	Operating Temperature		0 ~ 70
Tstg	Storage Temperature		-65 ~ 150

M2V56S40TP Features

· Single 3.3v±0.3V power supply
· Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
· Fully Synchronous operation referenced to clock rising edge
· Single Data Rate
· 4 bank operation controlled by BA0, BA1 (Bank Address)
· /CAS latency- 2/3 (programmable)
· Burst length- 1/2/4/8/full page (programmable)
· Burst type- sequential / interleave (programmable)
· Random column access
· Auto precharge / All bank precharge controlled by A10
· 8192 refresh cycles /64ms (4 banks concurrent refresh)
· Auto refresh and Self refresh
· Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
· LVTTL Interface
· 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

M2V56S40TP Connection Diagram

M2V56S40TP-6 General Description

M2V56S20TP is a 4-bank x 16777216-word x 4-bit, M2V56S30TP is a 4-bank x 8388608-word x 8-bit, M2V56S40TP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz (-6), and are suitable for main memory or graphic memory in computer systems.

M2V56S40TP-6 Maximum Ratings

Symbol	Parameter	Conditions	Ratings	Unit
Vdd	Supply Voltage	with respect to Vss	-0.5 ~ 4.6	V
VddQ	Supply Voltage for Output	with respect to VssQ	-0.5 ~ 4.6	V
VI	Input Voltage	with respect to Vss	-0.5 ~ Vdd+0.5	V
VO	Output Voltage	with respect to VssQ	-0.5 ~ VddQ+0.5	V
IO	Output Current		50	mA
Pd	Power Dissipation	Ta = 25 °C	1000	mW
Topr	Operating Temperature		0 ~ 70	°C
Tstg	Storage Temperature		-65 ~ 150	°C

M2V56S40TP-6 Features

- Single 3.3v±0.3V power supply
- Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

M2V56S40TP-6 Connection Diagram

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