Features: · Single 3.3V ±0.3V power supply· Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>· Fully synchronous operation referenced to clock rising edge· 4-bank operation controlled by BA0,BA1(Bank Address)· /CAS latency- 2/3 (programmable)· Burst length-...
M2V28S40ATP: Features: · Single 3.3V ±0.3V power supply· Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>· Fully synchronous operation referenced to clock rising edge· 4...
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Features: · Single 3.3V ±0.3V power supply· Max. Clock frequency -6:PC133<3 -3 -3> / -7:PC10...
Features: · Single 3.3V ±0.3V power supply· Max. Clock frequency -6:PC133<3 -3 -3> / -7:PC10...
Features: · Single 3.3V ±0.3V power supply· Max. Clock frequency -6:PC133<3-3-3> / -7:PC100&...
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
Vdd | Supply Voltage |
with respect to Vss |
-0.5 - 4.6 |
V |
VddQ | Supply Voltage for Output |
with respect to VssQ |
-0.5 - 4.6 |
V |
VI | Input Voltage |
with respect to Vss |
-0.5 - 4.6 |
V |
VO | Output Voltage |
with respect to VssQ |
-0.5 - 4.6 |
V |
IO | Output Current |
50 |
mA | |
Pd | Power Dissipation |
Ta = 25 |
1000 |
mW |
Topr | Operating Temperature |
0 ~ 70 |
||
Tstg | Storage Temperature |
-65 ~ 150 |
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.