M2V28S40ALT-6LL, M2V28S40ATP, M2V28S40ATP-6 Selling Leads, Datasheet
MFG:MIT Package Cooled:SSOP D/C:SSOP
M2V28S40ALT-6LL, M2V28S40ATP, M2V28S40ATP-6 Datasheet download
Part Number: M2V28S40ALT-6LL
MFG: MIT
Package Cooled: SSOP
D/C: SSOP
M2V28S40ALT-6LL, M2V28S40ATP, M2V28S40ATP-6
- Table of contents:
Info of M2V28S40ALT-6LL
Info of M2V28S40ATP
Info of M2V28S40ATP-6
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About M2V12D20TP
PDF/DataSheet Download
Datasheet: M2V12D20TP
File Size: 772135 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
About M2V28S40ATP
PDF/DataSheet Download
Datasheet: M2V28S40ATP
File Size: 641965 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
About M2V28S40ATP-6
PDF/DataSheet Download
Datasheet: M2V28S40ATP-6
File Size: 641965 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
M2V28S40ATP General Description
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.
M2V28S40ATP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
| Vdd | Supply Voltage |
with respect to Vss |
-0.5 - 4.6 |
V |
| VddQ | Supply Voltage for Output |
with respect to VssQ |
-0.5 - 4.6 |
V |
| VI | Input Voltage |
with respect to Vss |
-0.5 - 4.6 |
V |
| VO | Output Voltage |
with respect to VssQ |
-0.5 - 4.6 |
V |
| IO | Output Current |
50 |
mA | |
| Pd | Power Dissipation |
Ta = 25 |
1000 |
mW |
| Topr | Operating Temperature |
0 ~ 70 |
||
| Tstg | Storage Temperature |
-65 ~ 150 |
M2V28S40ATP Features
· Single 3.3V ±0.3V power supply
· Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
· Fully synchronous operation referenced to clock rising edge
· 4-bank operation controlled by BA0,BA1(Bank Address)
· /CAS latency- 2/3 (programmable)
· Burst length- 1/2/4/8/FP (programmable)
· Burst type- Sequential and interleave burst (programmable)
· Byte Control- DQML and DQMU (M2V28S40ATP)
· Random column access
· Auto precharge / All bank precharge controlled by A10
· Auto and self refresh
· 4096 refresh cycles /64ms
· LVTTL Interface
· Package M2V28S20ATP/30ATP/40ATP 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
· Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
· Fully synchronous operation referenced to clock rising edge
· 4-bank operation controlled by BA0,BA1(Bank Address)
· /CAS latency- 2/3 (programmable)
· Burst length- 1/2/4/8/FP (programmable)
· Burst type- Sequential and interleave burst (programmable)
· Byte Control- DQML and DQMU (M2V28S40ATP)
· Random column access
· Auto precharge / All bank precharge controlled by A10
· Auto and self refresh
· 4096 refresh cycles /64ms
· LVTTL Interface
· Package M2V28S20ATP/30ATP/40ATP 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
M2V28S40ATP Connection Diagram
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