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XCR3032, XCR3032-10VQ44C, XCR3032-12VQ44C

Table of contents:
Info of XCR3032
Info of XCR3032-10VQ44C
Info of XCR3032-12VQ44C

XCR3032, XCR3032-10VQ44C, XCR3032-12VQ44C Selling Leads, Datasheet

MFG:XILINX Package Cooled:PLCC44 D/C:09+

XCR3032, XCR3032-10VQ44C, XCR3032-12VQ44C Picture

XCR3032, XCR3032-10VQ44C, XCR3032-12VQ44C Datasheet download

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Part Number: XCR3032

MFG: XILINX

Package Cooled: PLCC44

D/C: 09+

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XCR3032 General Description

The XCR3032 CPLD (Complex Programmable Logic Device) is the first in a family of CoolRunner® CPLDs from Xilinx. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the XCR3032 offers true pin-to-pin speeds of 8 ns, while simultaneously delivering power that is less than 35 A at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Xilinx also offers the high speed XCR5032 CPLD that offers pin-to-pin speeds of 6 ns.

The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 8 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block.

This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 10.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.

The XCR3032 CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site).

The XCR3032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.

XCR3032 Maximum Ratings

Symbol	Parameter	Min.	Max.	Unit
V_CC	Supply voltage²	0.5	7.0	V
V_I	Input voltage	1.2	V_CC+0.5	V
V_OUT	Output voltage	0.5	V_CC +0.5	V
I_IN	Input current	30	30	mA
I_OUT	Output current	100	100	mA
T_J	Maximum junction temperature	-40	150
T_STG	Storage temperature	-65	150

Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied.
2. The chip supply voltage must be monotonic.

XCR3032 Features

• Industry's first TotalCMOS™ PLD - both CMOS design and process technologies
• Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
• High speed pin-to-pin delays of 8ns
• Ultra-low static power of less than 35 A
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• Two clocks available
• Programmable clock polarity at every macrocell
• Support for asynchronous clocking
• Innovative XPLA™ architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5 E²CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Xilinx CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
• Programmable global 3-state pin facilitates 'bed of nails' testing without using logic resources
• Available in both PLCC and VQFP packages

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