XCR22LV10

Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied..
2. Except F7, where max = V_CC + 0.5V.

The XCR22LV10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 5V operation, Xilinx offers the XCR22V10 that offers high speed and low power in a 5V implementation.

The XCR22LV10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This XCR22LV10 device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.