XCR22LV10-15VO24C, XCR22V10, XCR22V10 PC28ACM Selling Leads, Datasheet
MFG:XILINX D/C:07+
XCR22LV10-15VO24C, XCR22V10, XCR22V10 PC28ACM Datasheet download
Part Number: XCR22LV10-15VO24C
MFG: XILINX
Package Cooled:
D/C: 07+
MFG:XILINX D/C:07+
XCR22LV10-15VO24C, XCR22V10, XCR22V10 PC28ACM Datasheet download
MFG: XILINX
Package Cooled:
D/C: 07+
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Datasheet: XCR22LV10-15VO24C
File Size: 224044 KB
Manufacturer: XILINX [Xilinx, Inc]
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Datasheet: XCR22V10-10PC28C
File Size: 148917 KB
Manufacturer: Xilinx, Inc
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Datasheet: XCR-0
File Size: 22590 KB
Manufacturer:
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The XCR22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates.
This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Xilinx offers the XCR22LV10 that offers high speed and low power in a 3V implementation.
The XCR22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.
The XCR22V10 implements logic functions as sum-of-products expressions in a programmable -AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility (Figure 1).
Symbol | Parameter | Min. | Max. | Unit |
VCC | Supply voltage2 | 0.5 | 7.0 | V |
VI | Input voltage | 1.2 | VCC +0.5 | V |
VOUT | Output voltage | 0.5 | VCC +0.5 | V |
IIN | Input current | 30 | 30 | mA |
IOUT | Output current | 100 | 100 | mA |
TR | Allowale thermal rise ambient to junction | 0 | 75 | |
TJ | Maximum junction temperature | -40 | 150 | |
TSTG | Storage temperature | -65 | 150 | |
ESD | Static discharge voltage (human body) | - | 1000 | V |
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied..
• Industry's first TotalCMOS™ SPLD - both CMOS design and process technologies
• Fast Zero Power (FZP™) design technique provides ultra-low power and high speed
- Static current of less than 75 A
- Dynamic current substantially below that of competing devices
- Pin-to-pin delay of only 7.5 ns
• True Zero Power device with no turbo bits or power down schemes
• Function/JEDEC map compatible with Bipolar, UVCMOS, EECMOS 22V10s
• Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP)
- 24-pin TSOICuses 93% less in-system space than a 28-pin PLCC
- 24-pin SOIC
- 28-pin PLCC with standard JEDEC pinout
• Available in commercial and industrial operating ranges
• Advanced 0.5 E2CMOS process
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Varied product term distribution with up to 16 product terms per output for complex functions
• Programmable output polarity
• Synchronous preset/asynchronous reset capability
• Security bit prevents unauthorized access
• Electronic signature for identification
• Design entry and verification using industry standard CAE tools
• Reprogrammable using industry standard device programmers