UD61256DC, UD61256DC08, UD61464 Selling Leads, Datasheet
MFG:ZMD Package Cooled:DIP16 D/C:2008+
UD61256DC, UD61256DC08, UD61464 Datasheet download
Part Number: UD61256DC
MFG: ZMD
Package Cooled: DIP16
D/C: 2008+
UD61256DC, UD61256DC08, UD61464
- Table of contents:
Info of UD61256DC
Info of UD61256DC08
Info of UD61464
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About UD61256DC07
PDF/DataSheet Download
Datasheet: UD61256DC07
File Size: 227912 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About UD61256DC08
PDF/DataSheet Download
Datasheet: UD61256DC08
File Size: 227912 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About UD61464DC07
PDF/DataSheet Download
Datasheet: UD61464DC07
File Size: 179441 KB
Manufacturer:
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UD61464 General Description
Addressing
The UD61464 is a dynamic random access memory organized 65536 words by 4 bits. FPM facilitates faster data operation with predefined row address. Via 8 address inputs the 16 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address.
After the row address hold time the column address can be applied. The bit pattern that is available at the address outputs during the set-up time and after the falling edge of CAS is interpreted as row address. During Write the column address is taken over with the falling edge of the control signal CAS, or W, whichever becomes active as the last. The selection of one or more memory circuits can be made via the RAS input.
Read-Write-Control
The choice between Read or Write cycle is made at the W input. HIGH at the W input causes a Read cycle, meanwhile LOW leads to a Write cycle.
Both CAS-controlled and W-controlled Write cycles are possible with activated RAS signal.
UD61464 Maximum Ratings
| Absolute Maximum Ratings |
Symbol |
Min. |
Max. |
Unit |
| Power Supply Voltage Input Voltage 1) Output Voltage 1) Output Current 1a) Power Dissipation Operating Temperature Storage Temperature |
VCC VI VO IO PD Ta Tstg |
-0.5 -1.0 -1.0 -50 0 -55 |
7.0 7.0 7.0 50 1 70 125 |
V V V mA W °C °C |
UD61464 Features
· Dynamic random access memory 65536 x 4 bits manufactured using a CMOS technology
· RAS access times 70 ns/80 ns
· TTL-compatible
· Three-state outputs bidirectional
· 256 refresh cycles 4 ms refresh cycle time
· FAST PAGE MODE
· Operating modes: Read, Write, Read - Write, RAS only Refresh, Hidden Refresh with address transfer
· Low power dissipation
· Power supply voltage 5 V
· Package PDIP18 (300 mil)
· Operating temperature range 0 to 70 °C
· Quality assessment according to CECC 90000, CECC 90100 and CECC 90112
· RAS access times 70 ns/80 ns
· TTL-compatible
· Three-state outputs bidirectional
· 256 refresh cycles 4 ms refresh cycle time
· FAST PAGE MODE
· Operating modes: Read, Write, Read - Write, RAS only Refresh, Hidden Refresh with address transfer
· Low power dissipation
· Power supply voltage 5 V
· Package PDIP18 (300 mil)
· Operating temperature range 0 to 70 °C
· Quality assessment according to CECC 90000, CECC 90100 and CECC 90112
UD61464 Connection Diagram
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