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UD61466

Features: · Dynamic random access memory 65536 x 4 bits manufactured using a CMOS technology· RAS access times 70 ns/80 ns· TTL-compatible· Three-state outputs bidirectional· 256 refresh cycles 4 ms refresh cycle time· STATIC COLUMN MODE· Operating modes: Read, Write, Read - Write, RAS only Refres...

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SeekIC No. : 004536231 Detail

UD61466: Features: · Dynamic random access memory 65536 x 4 bits manufactured using a CMOS technology· RAS access times 70 ns/80 ns· TTL-compatible· Three-state outputs bidirectional· 256 refresh cycles 4 ms...

UD61466 Data Sheet

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Part Number:
UD61466
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·  Dynamic random access memory 65536 x 4 bits manufactured using a CMOS technology
·  RAS access times 70 ns/80 ns
·  TTL-compatible
·  Three-state outputs bidirectional
·  256 refresh cycles 4 ms refresh cycle time
·  STATIC COLUMN MODE
·  Operating modes: Read, Write, Read - Write, RAS only Refresh, Hidden Refresh with address transfer
·  Low power dissipation
·  Power supply voltage 5 V
·  Package PDIP18 (300 mil)
·  Operating temperature range 0 to 70 °C
·  Quality assessment according to CECC 90000, CECC 90100 and CECC 90112


Pinout

Connection Diagram


Specifications

Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage

Input Voltage 1)

Output Voltage 1)

Output Current 1a)

Power Dissipation

Operating Temperature

Storage Temperature
VCC

VI

VO

IO

PD

Ta

Tstg
-0.5

-1.0

-1.0

-50



0

-55
7.0

7.0

7.0

50

1

70

125
V

V

V

mA

W

°C

°C



Description

The UD61466 is a dynamic random access memory organized 65536 words by 4 bits.

SCM facilitates faster data operation with predefined row address. Via 8 address inputs the 16 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address. After the row address hold time the column address can be applied. During the Read cycle the address transfer is not latched by the falling edge at the CAS input, so that the column address must be applied until the data are valid at the output. During Write the column address is taken over with the falling edge of the control signal CAS, or W, that becomes active as the last. The selection of one or more memory circuits can be made via the RAS input.




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