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These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
NDP4060 Maximum Ratings
Symbol
Parameter
NDP4050
NDB4050
Units
VDSS
Drain-Source Voltage
60
V
VDGR
Drain-Gate Voltage (RGS 1 MW)
60
V
VGSS
Gate-Source Voltage - Continuous - Nonrepetitive (tP < 50 µs)
± 20
V
± 40
ID
Drain Current - Continuous - Pulsed
± 15
A
± 45
PD
Total Power Dissipation Derate above 25°C
50
W
0.33
W/
TJ,TSTG
Operating and Storage Temperature Range
-65 to 175
TL
Maximum lead temperature for soldering purposes,1/8" from case for 5 seconds
275
NDP4060 Features
`15A, 50V. RDS(ON) = 0.10 @ VGS=10V. `Critical DC electrical parameters specified at elevated temperature. `Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. `175°C maximum junction temperature rating. `High density cell design for extremely low RDS(ON). `TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.
NDP4060L Parameters
Technical/Catalog Information
NDP4060L
Vendor
Fairchild Semiconductor
Category
Discrete Semiconductor Products
Mounting Type
Through Hole
FET Polarity
N-Channel
Drain to Source Voltage (Vdss)
60V
Current - Continuous Drain (Id) @ 25° C
15A
Rds On (Max) @ Id, Vgs
80 mOhm @ 15A, 10V
Input Capacitance (Ciss) @ Vds
600pF @ 25V
Power - Max
50W
Packaging
Tube
Gate Charge (Qg) @ Vgs
17nC @ 5V
Package / Case
TO-220
FET Feature
Logic Level Gate
Lead Free Status
Lead Free
RoHS Status
RoHS Compliant
Other Names
NDP4060L NDP4060L
NDP4060L General Description
These logic level N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
NDP4060L Maximum Ratings
Symbol
Parameter
NDP4060L
NDB4060L
Units
VDSS
Drain-Source Voltage
60
V
VDGR
Drain-Gate Voltage (RGS 1 M)
60
V
VGSS
Gate-Source Voltage - Continuous - Nonrepetitive (tP < 50 µs)
± 16
V
± 25
ID
Drain Current - Continuous - Pulsed
15
A
45
PD
Total Power Dissipation @ TC = 25°C Derate above 25°C
50
W
0.33
W/
TJ,TSTG
Operating and Storage Temperature Range
-65 to 175
TL
Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
275
NDP4060L Features
`15A, 60V. RDS(ON) = 0.1 @ VGS = 5V `Low drive requirements allowing operation directly from logic drivers. VGS(TH) < 2.0V. `Critical DC electrical parameters specified at elevated temperature. `Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. `175°C maximum junction temperature rating. `High density cell design for extremely low RDS(ON). `TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.