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GS9000S, GS9001, GS9002

Table of contents:
Info of GS9000S
Info of GS9001
Info of GS9002

GS9000S, GS9001, GS9002 Selling Leads, Datasheet

MFG:GS Package Cooled:PLCC D/C:9911+

GS9000S, GS9001, GS9002 Datasheet download

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Part Number: GS9000S

MFG: GS

Package Cooled: PLCC

D/C: 9911+

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GS9001 General Description

The GS9001 implements error detection and handling (EDH) functions according to SMPTE RP165. Interfacing to the parallel port of either the GS9002/GS9022 serial digital encoders or GS9000 decoder, the GS9001 provides EDH insertion and extraction for 4fsc NTSC, 4fsc PAL and 4:2:2 component standards up to 18 MHz luminance sampling.

The GS9001 also generates timing signals such as horizontal sync, vertical blanking, field ID andancillary data identification. The ancillary data identification aids the extraction of ancillary data from the data stream.

The device has an I2C (Inter-Integrated Circuit) serial interface bus for communication with a microcontroller. The device can be programmed as an I2C slave transmitter or receiver by the microcontroller. This interface can be used to read the complete set of error flags and override the flag status prior to re-transmission. The device automatically determines the operating standard which can be overridden through the I2C interface. Timing signals and transmission error flags are also available on dedicated outputs.

GS9002 General Description

The GS9002 is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X⁹ + X⁴ +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100Mb/s to over 360Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines.

Other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The X⁹ + X⁴ + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers.

The GS9002 provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock.

The GS9002 directly interfaces with cable drivers GS9007, GS9008 and GS9009. The device requires a single +5 volt or -5 volt supply and typically consumes 713mW of power while driving 100 Ohm loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function.

GS9002 Maximum Ratings

PARAMETER	VALUE/UNITS
Supply Voltage	5.5 V
Input Voltage Range (any input)	-V_EE < V_I < V_CC
DC Input Current (any one input)	10 mA
Power Dissipation (V_S = 5.25 V)	1 W
Operating Temperature Range	0T_A70
Storage Temperature Range	-65T_S150
Lead Temperature (soldering 10 seconds)	260

GS9002 Features

·fully compatible with SMPTE-259M serial digital standard
·supports up to four serial bit rates to 400 Mb/s
·accepts 8 bit and 10 bit TTL and CMOS compatible parallel data inputs
·X⁹+ X⁴+ 1 scrambler, NRZI converter and sync detector may be disabled for transparent data
transmission
·pseudo-ECL serial data and clock outputs
·single +5 or -5 volt supply
·713 mW typical power dissipation (including ECL pull-down loads).
·44 pin PLCC packaging

GS9002 Typical Application

·4f _SC, 4:2:2 and 360 Mb/s serial digital interfaces for
Video cameras, VTRs, Signal generators NOT REC FOR N

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