Features: • fully compatible with SMPTE-259M serial digital standard• supports up to four serial bit rates to 400 Mb/s• accepts 8 bit and 10 bit TTL and CMOS compatible parallel data inputs• X9 + X4 + 1 scrambler, NRZI converter and sync detector may be disabled for transpa...
GS9002A: Features: • fully compatible with SMPTE-259M serial digital standard• supports up to four serial bit rates to 400 Mb/s• accepts 8 bit and 10 bit TTL and CMOS compatible parallel da...
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• fully compatible with SMPTE-259M serial digital standard
• supports up to four serial bit rates to 400 Mb/s
• accepts 8 bit and 10 bit TTL and CMOS compatible parallel data inputs
• X9 + X4 + 1 scrambler, NRZI converter and sync detector may be disabled for transparent data transmission
• pseudo-ECL serial data and clock outputs
• single +5 or -5 volt supply
• 713 mW typical power dissipation (including ECL pull-down loads).
• 44 pin PLCC packaging
• Pb-free and Green
PARAMETER |
VALUE/UNITS |
Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation (VS = 5.25 V) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10 seconds) |
5.5 V -VEE < VI < VCC 10 mA 1 W 0 TA 70 -65 TS 150 260 |
The GS9002A is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. GS9002A performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100 Mb/s to over 360 Mb/s.
The data rates of GS9002A are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines. Other features of GS9002A such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The X9 + X4 + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers.
The GS9002A provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock.
The GS9002A directly interfaces with cable drivers GS9007A, GS9008A and GS9009A. The device requires a single +5 volt or -5 volt supply and typically consumes 713 mW of power while driving 100 loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function.