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ZL50017QC, ZL50017QCENG2, ZL50018

Table of contents:
Info of ZL50017QC
Info of ZL50017QCENG2
Info of ZL50018

ZL50017QC, ZL50017QCENG2, ZL50018 Selling Leads, Datasheet

MFG:ZARLINK Package Cooled:03+04+ D/C:QFP

ZL50017QC, ZL50017QCENG2, ZL50018 Picture

ZL50017QC, ZL50017QCENG2, ZL50018 Datasheet download

Five Points

Part Number: ZL50017QC

MFG: ZARLINK

Package Cooled: 03+04+

D/C: QFP

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ZL50018 Maximum Ratings

	Parameter	Symbol	Min	Max	Units
1	I/O Supply Voltage	V _{DD_IO}	-0.5	5.0	V
2	Core Supply Voltage	V_{DD_CORE}	-0.5	2.5	V
3	Input Voltage	V _{I_3V}	-0.5	V_DD + 0.5	V
4	Input Voltage (5 V-tolerant inputs)	V _{I_5V}	-0.5	7.0	V
5	Continuous Current at Digital Outputs	I_o		15	mA
6	Package Power Dissipation	P_D		1.5	W
7	Storage Temperature	T_S	- 55	+125

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

ZL50018 Features

• 2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output streams
• Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 3 specifications
• Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output)
• DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs
• Programmable key DPLL parameters (filter corner frequency, locking range, auto-holdover hysteresis range, phase slope, lock detector range)
• Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates)
• Output streams can be configured as bidirectional for connection to backplanes
• Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and output data rates can differ
• Per-stream high impedance control outputs (STOHZ) for up to 16 output streams
• Per-stream input bit delay with flexible sampling point selection
• Per-stream output bit and fractional bit advancement
• Per-channel ITU-T G.711 PCM A-Law/-Law Translation
• Multiple frame pulse and reference clock output
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per Stream Bit Error Rate Test circuits
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage

ZL50018 Typical Application

• PBX and IP-PBX
• Small and medium digital switching platforms
• Wireless base stations and controllers
• Remote access servers and concentrators
• Multi service access platforms
• Digital Loop Carriers
• Computer Telephony Integration

ZL50018 Connection Diagram

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