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ZL50016, ZL50016GA, ZL50016QC

Table of contents:
Info of ZL50016
Info of ZL50016GA
Info of ZL50016QC

ZL50016, ZL50016GA, ZL50016QC Selling Leads, Datasheet

MFG:MT Package Cooled:BGA D/C:05+

ZL50016, ZL50016GA, ZL50016QC Datasheet download

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Part Number: ZL50016

MFG: MT

Package Cooled: BGA

D/C: 05+

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ZL50016 General Description

The ZL50016 is a maximum 1024 x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch. It has sixteen input streams (STi0 - 15) and sixteen output streams (STio0 - 15). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The ZL50016 provides up to eight high impedance control outputs (STOHZ0 - 7) to support the use of external tristate drivers for the first eight output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 15 will be ignored.

The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 16 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 16 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state.

The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors.

The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.

ZL50016 Maximum Ratings

	Parameter	Symbol	Min	Max	Units
1	I/O Supply Voltage	V _{DD_IO}	-0.5	5.0	V
2	Core Supply Voltage	V _{DD_CORE}	-0.5	2.5	V
3	Input Voltage	V _{I_3V}	-0.5	VDD + 0.5	V
4	Input Voltage (5 V-tolerant inputs)	V _{I_5V}	-0.5	7.0	V
5	Continuous Current at Digital Outputs	I_o		15	mA
6	Package Power Dissipation	P_D		1.5	W
7	Storage Temperature	T_S	- 55	+125

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

ZL50016 Features

• 1024 channel x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch at 4.096 Mbps, 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps
• 16 serial TDM input, 16 serial TDM output streams
• Output streams can be configured as bidirectional for connection to backplanes
• Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates)
• Per-stream input and output data rate conversion selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Input and output data rates can differ
• Per-stream high impedance control outputs (STOHZ) for 8 output streams
• Per-stream input bit delay with flexible sampling point selection
• Per-stream output bit and fractional bit advancement
• Per-channel ITU-T G.711 PCM A-Law/-Law Translation
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses:61 ns, 122 ns, 244 ns
• Four frame pulse and four reference clock outputs
• Three programmable delayed frame pulse outputs
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per Stream (16) Bit Error Rate Test circuits complying to ITU-O.151
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage

ZL50016 Typical Application

• PBX and IP-PBX
• Small and medium digital switching platforms
• Remote access servers and concentrators
• Wireless base stations and controllers
• Multi service access platforms
• Digital Loop Carriers
• Computer Telephony Integration

ZL50016 Connection Diagram

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