VG3617161BT-8, VG3617161DT, VG3617161DT-7 Selling Leads, Datasheet
MFG:VANGUARO Package Cooled:04+ D/C:00+
VG3617161BT-8, VG3617161DT, VG3617161DT-7 Datasheet download
Part Number: VG3617161BT-8
MFG: VANGUARO
Package Cooled: 04+
D/C: 00+
VG3617161BT-8, VG3617161DT, VG3617161DT-7
- Table of contents:
Info of VG3617161BT-8
Info of VG3617161DT
Info of VG3617161DT-7
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About VG3617161BT-8
PDF/DataSheet Download
Datasheet: VG3617161BT-8
File Size: 1644753 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About VG3617161DT
PDF/DataSheet Download
Datasheet: VG3617161DT
File Size: 965989 KB
Manufacturer: VML [Vanguard International Semiconductor]
Download : Click here to Download
About VG3617161DT-7
PDF/DataSheet Download
Datasheet: VG3617161DT-7
File Size: 965989 KB
Manufacturer: VML [Vanguard International Semiconductor]
Download : Click here to Download
VG3617161DT General Description
The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed application.Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
VG3617161DT Maximum Ratings
| Parameter | Symbol | Value | Unit |
| Voltage on any pin relative to Vss |
VIN,VOUT | -1.0 to +4.6 | V |
| Supply voltage relative to Vss | VDD,VDDQ | -1.0 to +4.6 | V |
| Short circuit output current | IOUT | 50 | mA |
| Power dissipation | PD | 1.0 | W |
| Operating temperature | TOPT | 0 to + 70 | · |
| Storage temperature | TSTG | -55 to + 125 | · |
VG3617161DT Features
• Single 3.3V +/- 0.3V power supply
• Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz
• Fully synchronous with all signals referenced to a positive clock
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual internal banks controlled by A11(Bank select)
• Simultaneous and independent two bank operation
• I/O level : LVTTL interface
• Random column access in every cycle
• X16 organization
• Byte control by LDQM and UDQM
• 4096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz
• Fully synchronous with all signals referenced to a positive clock
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual internal banks controlled by A11(Bank select)
• Simultaneous and independent two bank operation
• I/O level : LVTTL interface
• Random column access in every cycle
• X16 organization
• Byte control by LDQM and UDQM
• 4096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
VG3617161DT Connection Diagram
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