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The TH50VSF3582/3583AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a33,554,432-bit flash memory. The CIOS andCIOF inputs can be used to select the optimal memory configuration.The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Writeor Erase operation. The TH50VSF3582/3583AASB can range from 2.67 V to 3.3 V. The TH50VSF3582/3583AASB isavailable in a 69-pin BGA package, making it suitable for a variety of design applications.
TH50VSF3583AASB Maximum Ratings
SYMBOL
PARAMETER
RANGE
UNIT
VCC
VCCs/VCCf Supply Voltage
−0.3~4.2
V
VIN
Input Voltage(1)
−0.3~4.2
V
VDQ
Input/Output Voltage
−0.5~VCC + 0.5 ( 4.2)
V
Topr
Operating Temperature
−20~85
°C
PD
Power Dissipation
0.6
W
Tsolder
Soldering Temperature (10 s)
260
°C
IOSHORT
Output Short Circuit Current(2)
100
mA
NEW
Erase/Program Cycling Capability
100,000
Cycle
Tstg
Storage Temperature
−55~125
°C
TH50VSF3583AASB Features
• Power supply voltageVCCs = 2.67 V~3.3 VVCCf = 2.67 V~3.3 V • Data retention supply voltageVCCs = 1.5 V~3.3 V • Current consumptionOperating: 45 mA maximum (CMOS level)Standby: 10 A maximum (SRAM CMOS level)Standby: 10 A maximum (FLASH) • Block erase architecture for flash memory8 * 8 Kbytes63 * 64 Kbytes • Function mode control for flash memoryCompatible with JEDEC-standard commands • Flash memory functionsSimultaneous Read/Write operationsAuto-ProgramAuto Chip Erase, Auto Block EraseAuto Multiple-Block EraseProgram Suspend/ResumeBlock-Erase Suspend/ResumeData Polling/Toggle Bit functionBlock Protection/Boot Block ProtectionAutomatic Sleep, Hidden ROM Area SupportsCommon Flash Memory Interface (CFI)Byte/Word Mode • Erase and Program cycle for flash memory105 cycles (typical) • Boot block architecture for flash memoryTH50VSF3582AASB: Top boot blockTH50VSF3583AASB: Bottom boot block • PackageP-FBGA69-1209-0.80A3: 0.31 g (typ.)