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TH50VSF1421ACXB, TH50VSF1480AASB(EL), TH50VSF2581AASB

TH50VSF1421ACXB, TH50VSF1480AASB(EL), TH50VSF2581AASB Selling Leads, Datasheet

MFG:BGA8*17  Package Cooled:1360  D/C:TOS

TH50VSF1421ACXB, TH50VSF1480AASB(EL), TH50VSF2581AASB Picture

TH50VSF1421ACXB, TH50VSF1480AASB(EL), TH50VSF2581AASB Datasheet download

Five Points

Part Number: TH50VSF1421ACXB

 

MFG: BGA8*17

Package Cooled: 1360

D/C: TOS

 

 

 
 
 
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TH50VSF1421ACXB Suppliers

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About TH50VSF1480

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Datasheet: TH50VSF1480

File Size: 1194112 KB

Manufacturer: Toshiba Semiconductor

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TH50VSF1480AASB(EL) Suppliers

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About TH50VSF1480

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Datasheet: TH50VSF1480

File Size: 1194112 KB

Manufacturer: Toshiba Semiconductor

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TH50VSF2581AASB Suppliers

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About TH50VSF2581AASB

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Datasheet: TH50VSF2581AASB

File Size: 559829 KB

Manufacturer: TOSHIBA [Toshiba Semiconductor]

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TH50VSF2581AASB General Description

The TH50VSF2580/2581AASB is a mixed multi-chip package containing a 4,194,304-bit full CMOS SRAM and a 33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply for the TH50VSF2580/2581AASB can range from 2.7 V to 3.6 V. The TH50VSF2580/2581AASB can perform simultaneous read/write operations on its flash memory and is available in a 69-pin BGA package, making it suitable for a variety of applications.

TH50VSF2581AASB Maximum Ratings

SYMBOL PARAMETER RANGE UNIT
VCC VCCs/VCCf Supply Voltage −0.3~4.6 V
VIN Input Voltage(1) −0.3~4.6􀃧 V
VDQ Input/Output Voltage −0.5~VCC + 0.5 ( 4.6) V
Topr Operating Temperature -40~85 °C
PD Power Dissipation 0.6 W
Tsolder Soldering Temperature (10s) 260 °C
IOSHORT Output Short Circuit Current(2) 100 mA
NEW Erase/Program Cycling Capability 100,000 Cycles
Tstg Storage Temperature −55~125 °C

TH50VSF2581AASB Features

• Power supply voltage
   VCCs = 2.7 V~3.6 V
   VCCf = 2.7 V~3.6 V
• Data retention supply voltage
   VCCs = 1.5 V~3.6 V
• Current consumption
   Operating: 45 mA maximum (CMOS level)
   Standby: 7 A maximum (SRAM CMOS level)
   Standby: 10 A maximum (flash CMOS level)
• Block erase architecture for flash memory
   8 blocks of 8 Kbytes
   63 blocks of 64 Kbytes
• Organization
• Function mode control for flash memory
   Compatible with JEDEC-standard commands
• Flash memory functions
   Simultaneous Read/Write operations
   Auto-Program
   Auto Chip Erase, Auto Block Erase
   Auto Multiple-Block Erase
   Program Suspend/Resume
   Block-Erase Suspend/Resume
   Data Polling / Toggle Bit function
   Block Protection / Boot Block Protection
   Support for automatic sleep and hidden ROM area
   Common flash memory interface (CFI)
   Byte/Word Modes
• Erase and Program cycles for flash memory
   105 cycles (typical)
• Boot block architecture for flash memory
   TH50VSF2580AASB: Top boot block
   TH50VSF2581AASB: Bottom boot block
• Package
   P-FBGA69-1209-0.80A3: 0.31 g (typ.)

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