MFG:Micrel Inc Category:Integrated Circuits (ICs) Package Cooled:PLCC D/C:09+
SY100E106JC, SY100E107JZ, SY100E111 Datasheet download
Category: Integrated Circuits (ICs)
MFG: Micrel Inc
Package Cooled: PLCC
D/C: 09+
Description: IC GATE XOR/XNOR QUINT 28-PLCC
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PDF/DataSheet Download
Datasheet: SY10
File Size: 80720 KB
Manufacturer: SEMTECH [Semtech Corporation]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SY100E107JZTR
File Size: 63059 KB
Manufacturer: MICREL [Micrel Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SY100E111
File Size: 93231 KB
Manufacturer: MICREL [Micrel Semiconductor]
Download : Click here to Download
| Technical/Catalog Information | SY100E107JZ |
| Vendor | Micrel Inc |
| Category | Integrated Circuits (ICs) |
| Number of Circuits | 5 |
| Logic Type | 2 Input XOR/XNOR |
| Current - Output High, Low | - |
| Output Type | Differential |
| Schmitt Trigger Input | No |
| Voltage - Supply | 4.2 V ~ 5.5 V |
| Operating Temperature | 0°C ~ 85°C |
| Number of Inputs | 2 |
| Mounting Type | Surface Mount |
| Package / Case | 28-PLCC |
| Packaging | Bulk |
| Drawing Number | * |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | SY100E107JZ SY100E107JZ 576 2428 ND 5762428ND 576-2428 |
The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or single-ended input, with VBB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH.
The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of "basic" processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay.
To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. ln most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew.
The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using VBB for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor.
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