SY100E111L

Features: 5V and 3.3V power supply options 200ps part-to-part skew 50ps output-to-output skew Differential design VBB output Voltage and temperature compensated outputs 75K input pulldown resistors Fully compatible with Motorola MC100LVE111 Available in 28-pin PLCC packagePinoutDescriptionThe SY1...

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SeekIC No. : 004509861 Detail

SY100E111L: Features: 5V and 3.3V power supply options 200ps part-to-part skew 50ps output-to-output skew Differential design VBB output Voltage and temperature compensated outputs 75K input pulldown resistors...

floor Price/Ceiling Price

Part Number:
SY100E111L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

5V and 3.3V power supply options
200ps part-to-part skew
50ps output-to-output skew
Differential design
VBB output
Voltage and temperature compensated outputs
75K input pulldown resistors
Fully compatible with Motorola MC100LVE111
Available in 28-pin PLCC package



Pinout

  Connection Diagram


Description

The SY10/SY100E111L/L are low skew 1-to-9 differential driver designed for clock distribution in mind. The SY10/SY100E111L/L's function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts one signal input, which can be either Differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The SY100E111L/L are specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

To ensure that the tight skew specification is met SY100E111L is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer that nine pairs are used,it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side,in order to maintain minimum skew.Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.The SY100E111L/L, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the SY100E111L/L to be used for high performance clock distribution in +5V/+3.3V systems. Designers can take advantage of the SY100E111L/L's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies.For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2V supply as terminating voltage.




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