MFG:VISHAY Package Cooled:. D/C:06+07+pb-free
SUM110N03-03, SUM110N03-03P, SUM110N03-04P Datasheet download
MFG: VISHAY
Package Cooled: .
D/C: 06+07+pb-free
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PDF/DataSheet Download
Datasheet: SUM110N03-03
File Size: 42298 KB
Manufacturer: VISAY [Vishay Siliconix]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SUM110N03-03P
File Size: 186217 KB
Manufacturer: VISAY [Vishay Siliconix]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SUM09MN20-270
File Size: 40516 KB
Manufacturer: VISAY [Vishay Siliconix]
Download : Click here to Download
| ABSOLUTE MAXIMUM RATINGS (TC = 25 UNLESS OTHERWISE NOTED) | ||||
|
Parameter |
Symbol | Limit | Unit | |
| Drain-Source Voltage | VDS | 30 | V | |
| Gate-Source Voltage | VGS | ±20 | ||
| Continuous Drain Current (TJ = 175) |
TC = 25 | ID | 110a | A |
| TC = 100 | 110a | |||
| Pulsed Drain Current | IDM | 350 | ||
| Avalanche Current | IAR | 70 | ||
| Repetitive Avalanche Energyb | L = 0.1 mH | EAR | 245 | mJ |
| Maximum Power Dissipationb | TC = 25 | PD | 242c | W |
| TA = 25d | 3.75 | |||
| Operating Junction and Storage Temperature Range | TJ, Tstg | −55 to 175 | ||
The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
| SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
| Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
| Static | |||||
| Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 A | 1.8 | V | |
| On-State Drain Currenta | ID(on) | VDS = 5 V, VGS = 10 V | 1708 | A | |
| Drain-Source On-State Resistancea | rDS(on) | VGS = 10 V, ID = 30 A | 0.0019 | 0.0022 | Ω |
| VGS = 10 V, ID = 30A, TJ = 125°C | 0.0026 | ||||
|
VGS = 4.5V, ID =20A |
0.0030 | 0.0031 | |||
| Forward Voltagea | VSD | IS = 110A, VGS = 0 V | 0.93 | 1.1 | V |
| Dynamicb | |||||
| Input Capacitance | Ciss | VGS = 0 V, VDS = 25 V, f = 1 MHz | 11410 | 12100 | pF |
| Output Capacitance | Coss | 811 | 1910 | ||
| Reverse Transfer Capacitance | Crss | 489 | 1250 | ||
| Total Gate Chargec | Qg | VDS = 15 V, VGS = 10 V, ID = 110 A | 194 | 172 | nC |
| Gate-Source Chargec | Qgs | 40 | 40 | ||
| Gate-Drain Chargec | Qgd | 40 | 22 | ||
| Turn-On Delay Timec | td(on) | VDD = 15V, RL = 0.18Ω ID= 110A, VGEN = 10 V, RG = 2.5 Ω |
19 | 20 | ns |
| Rise Timec | tr | 23 | 20 | ||
| Turn-Off Delay Timec | td(off) | 50 | 90 | ||
| Fall Timec | tf | 44 | 25 | ||
| Source-Drain Reverse Recovery Time | trr | IF = 85 A, di/dt = 100 A/µs | 31 | 60 | |
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