Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 1.8 V On-State Drain Currenta ID(on) VDS = 5 V, VGS = 10 V 1708 A Drain...
SUM110N03-03P: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...
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Features: `TrenchFET® Power MOSFET` 175 Junction Temperature`Optimized for Low-Side Synchronou...
Features: `TrenchFET®Power MOSFET` 175 Junction Temperature` Low Thermal Resistance Package` H...
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
Static | |||||
Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 A | 1.8 | V | |
On-State Drain Currenta | ID(on) | VDS = 5 V, VGS = 10 V | 1708 | A | |
Drain-Source On-State Resistancea | rDS(on) | VGS = 10 V, ID = 30 A | 0.0019 | 0.0022 | Ω |
VGS = 10 V, ID = 30A, TJ = 125°C | 0.0026 | ||||
VGS = 4.5V, ID =20A |
0.0030 | 0.0031 | |||
Forward Voltagea | VSD | IS = 110A, VGS = 0 V | 0.93 | 1.1 | V |
Dynamicb | |||||
Input Capacitance | Ciss | VGS = 0 V, VDS = 25 V, f = 1 MHz | 11410 | 12100 | pF |
Output Capacitance | Coss | 811 | 1910 | ||
Reverse Transfer Capacitance | Crss | 489 | 1250 | ||
Total Gate Chargec | Qg | VDS = 15 V, VGS = 10 V, ID = 110 A | 194 | 172 | nC |
Gate-Source Chargec | Qgs | 40 | 40 | ||
Gate-Drain Chargec | Qgd | 40 | 22 | ||
Turn-On Delay Timec | td(on) | VDD = 15V, RL = 0.18Ω ID= 110A, VGEN = 10 V, RG = 2.5 Ω |
19 | 20 | ns |
Rise Timec | tr | 23 | 20 | ||
Turn-Off Delay Timec | td(off) | 50 | 90 | ||
Fall Timec | tf | 44 | 25 | ||
Source-Drain Reverse Recovery Time | trr | IF = 85 A, di/dt = 100 A/µs | 31 | 60 |
The attached spice model of SUM110N03-03P describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUM110N03-03P is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of SUM110N03-03P is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUM110N03-03P.