SUD17N25-16S, SUD19N20-90, SUD19P06-60L Selling Leads, Datasheet
MFG:VISHAY Package Cooled:SOT-252 D/C:2006
SUD17N25-16S, SUD19N20-90, SUD19P06-60L Datasheet download
Part Number: SUD17N25-16S
MFG: VISHAY
Package Cooled: SOT-252
D/C: 2006
MFG:VISHAY Package Cooled:SOT-252 D/C:2006
SUD17N25-16S, SUD19N20-90, SUD19P06-60L Datasheet download
MFG: VISHAY
Package Cooled: SOT-252
D/C: 2006
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PDF/DataSheet Download
Datasheet: SUD06N10-225L
File Size: 67234 KB
Manufacturer: VISAY [Vishay Siliconix]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SUD19N20-90
File Size: 49680 KB
Manufacturer: VISAY [Vishay Siliconix]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SUD19P06-60L
File Size: 186410 KB
Manufacturer: VAISH [Vaishali Semiconductor]
Download : Click here to Download
ABSOLUTE MAXIMUM RATINGS (TC = 25 UNLESS OTHERWISE NOTED) | ||||
Parameter |
Symbol | Limit | Unit | |
Drain-Source Voltage | VDS | 200 | V | |
Gate-Source Voltage | VGS | ±20 | ||
Continuous Drain Current(TJ = 175)b | TC = 25 | ID | 19 | A |
TC = 125 | 11 | |||
Pulsed Drain Current | IDM | 40 | ||
Continuous Source Current (Diode Conduction) |
IS |
19 | ||
Avalanche Current | IAR | 19 | ||
Repetitive Avalanche Energy (Duty Cycle 1%) | L = 0.1 mH | EAR | 18 | mJ |
Maximum Power Dissipationa | TC = 25 | PD | 100b | W |
TA = 25 | 3a | |||
Operating Junction and Storage Temperature Range | TJ, Tstg | -55 to 175 |
The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
Static | |||||
Gate Threshold Voltage | VGS(th) | VDS = VGS, ID =- 250 A | 2 | V | |
On-State Drain Currenta | ID(on) | VDS = -5 V, VGS = -10 V | 104 | A | |
Drain-Source On-State Resistancea | rDS(on) | VGS = -10 V, ID = -10 A | 0.047 | 0.047 | Ω |
VGS = -10 V, ID =-10 A, TJ = 125°C | 0.083 | ||||
VGS = -10 V, ID = -10A, TJ = 175°C | 0.102 | ||||
VGS = −4.5 V, ID = −5 A | 0.060 | 0.061 | |||
Forward Transconductance a | gfs |
VGS = -15V, ID =-10 A |
20 | 22 |
S |
Forward Voltagea | VSD | IS = -10 A, VGS = 0 V | -0.87 | -1 | V |
Dynamicb | |||||
Input Capacitance | Ciss | VGS = 0 V, VDS = -25 V, f = 1 MHz | 1430 | 1140 | pF |
Output Capacitance | Coss | 130 | 130 | ||
Reverse Transfer Capacitance | Crss | 84 | 90 | ||
Total Gate Chargec | Qg | VDS = -30 V, VGS = -10 V, ID = -10 A | 25 | 26 | nC |
Gate-Source Chargec | Qgs | 4.5 | 4.5 | ||
Gate-Drain Chargec | Qgd | 7 | 7 |